Information Technology Reference
In-Depth Information
2
The System Simulator
We very briefly describe the key features of our integrated system simulator as
background information; it is comprised of a CPU simulator, an OS simulator and
a high-level 'teaching language' compiler [1] all integrated in one single package.
The tutorial notes guide our students to becoming familiar with and proficient in
the simulators in progressive stages throughout their three-year degree course.
The CPU simulator simulates RISC type architecture; it has a small set of CPU
instructions, a large register file and incorporates a five-stage pipeline simulator as
well as Harvard style separate data and instruction cache simulators.
The OS simulator supports two main aspects of a computer system's resource
management: process management and memory management. The process sche-
duler supports several scheduling mechanisms. Threads, mutual exclusion, process
synchronization and deadlock concepts are explored via teaching language con-
structs; the virtual memory simulations explore the principles of address transla-
tion, paging, placement and replacement concepts.
The 'teaching' compiler demonstrates the generation of low-level CPU instruc-
tions and explores key instruction optimization methods.
3
The Visualizations
In this section we look at examples of visualization techniques used in our simula-
tions. As over 90% of our students are visual learners we feel justified in our ef-
forts in this area. While the simulations support and complement the theory they
also need to be engaging and involving. To this end we therefore suitably adopted
the principles identified in the 'Taxonomy of Engagement' [2] by the working
group on the impact of algorithm visualizations while paying careful consideration
to 'Blooms Taxonomy' of educational objectives [3]. Our efforts in this are further
explored in [4] where we present our evaluation methods and the results.
3.1
CPU Simulator Visualizations
There are three areas of CPU architecture that particularly lend themselves to vi-
sualization and animation: instruction execution, caching and pipelining technolo-
gies. The CPU simulator demonstrates the main functions of a typical CPU by
employing several visualization methods. It does this by presenting views of in-
structions in memory, data in stack and in CPU registers as shown in Figure 1.
The execution of CPU instructions are visually enhanced by highlighting instruc-
tions as they are executed and by animating the instances of updating data in regis-
ters and on the program stack as and when these areas are accessed.
Advanced CPU simulator features include a 5-stage pipeline simulator, data
and instruction cache simulators. The individual stages of the pipeline are
represented as blocks of different colors. The pipeline can be switched on or off
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