Biomedical Engineering Reference
In-Depth Information
Fig. 5.1
Circuit with stuck-at
fault
1
a
0/1
s−a−1
0
0
b
0/1
c
(s-a-1 and s-a-0, respectively). Thus, a net with a stuck-at-0 fault will always have a
logic value 0, irrespective of the correct logic output of the gate (gene) driving the net.
As an example, consider the circuit of Fig.
5.1
comprising of an OR gate driving
an AND gate. Also consider a stuck-at-1 fault at the output of the OR gate, which
means that the faulty line remains 1 irrespective of the input state of the OR gate.
If the normal (good) output of the OR gate is 1 (in the case where its inputs were
<bc>
01, 10, 11), then this fault will not affect any signal in the circuit. However,
the input
<bc>
=
00 to the OR gate should produce a 0 output in the good circuit.
For this input, the good (faulty) value 0 (1) is applied to the AND gate. If the input
vector
<abc>
=
100, the good circuit output (true response) and faulty output
would differ. Hence
<abc>
=
=
100 is called a test for the s-a-1 fault on the output
of the OR gate.
A stuck-at-0 fault is modeled by inserting a two-input AND gate and an inverter
at the fault site as shown in Fig.
5.2
. The side input of the gate is driven by a signal
which is set to 0 to simulate a fault-free condition, or set to 1 to inject the s-a-0 fault.
Similarly, the circuit with a s-a-1 fault is modeled by inserting an OR gate at the
condition. The side input of this OR gate is set to 0 to simulate a fault-free site, or
set to 1 to inject the s-a-1 fault. These gates are inserted at every net (wire), allowing
the simulator to inject faults at any site.
Note that drugs are modeled the same as stuck-at faults, wherein a drug that
inhibits a gene is modeled as a s-a-0 “fault”, while a drug that activates a gene is
modeled as s-a-1 “fault”. The gates for drug injection are inserted at the nets of the
genes that they are known to target.
5.3.3
SAT-based Formulation for Stuck-at Fault Model
In the SAT based ATPG method, we first generate a formula in CNF to represent tests
for the fault. To do so, the circuit from the stuck-at fault model must be converted to
a CNF. Every gate (
g
i
) of the circuit has CNF formula (
G
i
) associated with it, which
represent the function performed by the gate. The formula is true if and only if the
variables representing the gate's inputs and outputs take on values consistent with
its truth table.
For example, consider a 2-input AND gate (
g
j
) with the lines
x
and
y
as inputs
and
z
as output. The CNF formula (
G
j
) for the AND gate is written as shown below
