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is the average number of bit transitions (switching activity) on the bus caused
by transfer of
N
bit patterns.
HD
(
d
t
,d
t
+1
) is the Hamming Distance between
two consecutive bit patterns
d
t
and
d
t
+1
. The present work reduces
n
trans
on
the address bus of data memory. This work focuses on systems that use Harvard
architecture employing independent data and instruction address buses. This
work considers the address bus between L1-data cache and the processor, where
the L1-data cache is on-chip. The present work exploits the sequential access of
adjacent memory locations, when a set of sequential locations (like an array) is
initialized within a small loop, and introduces loop unrolling with partial Gray
code sequence. This technique reduces on-chip bus switching activity on the ad-
dress bus of data memory, thereby saving energy. The proposed work does not
require any extra hardware for encoding and decoding address on the address
bus. Programmers and/or compilers can exploit this idea to reduce switching ac-
tivity on address bus of data memory, when they encounter loops which initialize
array of considerable size. Loop unrolling reduces the number of loop manipu-
lation instructions by loop unrolling factor (
uf
) saving both time and energy.
Array initialization using loop unrolling with partial Gray code sequence can
save more energy by reducing switching activity on the address bus of on-chip
L1-data cache.
1.1 Related Work
Several hardware based approaches to reduce bus switching activity has been
proposed earlier which require extra hardware in the form of encoders and de-
coders which consume more silicon space (increasing the design cost), power
and degrades performance. Since, the present work is a software based tech-
nique, the hardware approaches are not discussed. In [4] the authors proposed
the idea for instruction scheduling to reduce switching activity. The authors of
[5] studied Gray code addressing to reduce switching activity on the instruc-
tion address bits and introduced an instruction scheduling technique called cold
scheduling to reorder instruction sequence to reduce the switching activities.
In [6,7] Lee et al proposed a greedy bipartite-matching instruction scheduling
scheme to reduce switching activity in the instruction bus. In [8] Parikh et al
proposed instruction scheduling algorithms considering the activity of switching
from one instruction to another instruction as circuit-state effect (circuit-state
cost or inter-instruction cost). In [9] the authors proposed an algorithm to re-
duce both schedule length by 11.5% and bus-switching activities by an average
of 19.4% for applications with loops. In [11] the authors proposed an algorithm
to reduce bus-switching activities by 52.2% and schedule length by an average of
20.1% while performing scheduling and allocation simultaneously. The method
proposed in [10] modifies operation placement orders within VLIW instructions
to reduce the switching activity between successive instruction fetches by 34%
on an average.
