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Energy Ecient Array Initialization Using Loop
Unrolling with Partial Gray Code Sequence
Sumanta Pyne and Ajit Pal
Department of Computer Science and Engineering
Indian Institute of Technology Kharagpur, West Bengal, 721 302, India
{
spyne,apal
}
@cse.iitkgp.ernet.in
Abstract.
The present work introduces a software technique to reduce
energy consumed by the address bus of the on-chip data memory. This
is done by reducing switching activity on the address bus of the on-chip
data memory, with the help of loop unrolling with partial Gray code se-
quence. The present work introduces the translation of a loop with array
initialization to its loop unrolled version with partial Gray code sequence.
The expressions for switching activity consumed on the address bus of
data memory are derived for both unrolled loop with and without partial
Gray code sequence. The proposed translation method finds a relocat-
able base address of the array so that the partial Gray code sequence
is maintained, without any energy-performance overhead and achieves a
considerable amount of energy reduction without any performance loss.
The proposed method achieves 25-50% reduction in switching activity on
the address bus of on-chip data memory. The present work is evaluated
on five benchmark programs and is suitable for programs where array
initialization time is more than computation time.
Keywords:
Energy reduction, array initialization, address bus of on-
chip L1-data cache, switching activity, loop unrolling, unrolling factor,
loop unrolling with partial Gray code sequence, translation.
1 Introduction
Energy/power consumed by VLSI circuits is directly proportional to the switch-
ing activity. The address and data bus connecting memory and processor are
highly capacitive which leads to the switching power dissipation when 0
−
to
−
1
and 1
0 bit transitions occur on the buses at high frequency. As the
technology scales down to the deep-submicron region, the inter-wire capacitance
(
C
I
) becomes significant compared to the wire-to-substrate capacitance (
C
L
).
As
C
I
is the dominant capacitance in deep sub-micron era, it has two signif-
icant effects, large propagation delay due to opposite transitions on adjacent
wires [1,2,3] and power dissipation associated with driving the on-chip buses
[2]. The expression for average bus wire power consumption can be written as
P
avg
=
2
×
−
to
−
V
dd
×
f
where,
C
bus
is the bus capacitance,
V
dd
is the
supply voltage,
f
is the frequency of operation.
n
trans
=
N−
1
C
bus
×
n
trans
×
t
=0
HD
(
d
t
,d
t
+1
)
N
,which
