Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization - VLSI Design and Test - page 81

Tabl e 4. Non-preemptive Vs. Mixed scheduling result (10% cores are being
preemptive)

SoC Number of I/O ports

(2,2) (3,3) (4,4)

Non Mixed Non Mixed Non Mixed

preemptive [3] preemptive [3] preemptive [3]

d695(10) 19618 19618 13868 13238 10545 10104

g1023(14) 29148 29117 19277 18880 14794 14794

p22810(28) 290125 290125 188695 187800 162951 141630

p34392(19) 263172 263172 184387 176322 162626 162626

p93791(32) 318199 318199 207003 204424 155148 150200

t512505(31) 500222 500222 330685 330579 250631 249130

in most of the cases, preemptive scheduling could utilize the idle time slots left
otherwise by a non-preemptive schedule, thus reducing the overall test time. Out
of 18 test cases, in 11 cases (shown in bold in Table 4) preemptive schedule could
obtain better test times.

7Con lu on

This approach shows a new way to test the core-based SoC system in NoC envi-
ronment. It is a combination of both non-preemptive and preemptive scheduling
approach. In preemptive scheduling approach test session for each core is divided
into multiple number of test sessions whereas in non-preemptive scheduling a sin-
gle test session is devoted for each core. Experimental results for ITC'02 bench-
marks show that our approach outperforms other works presented in [2] and [3].
This work can extended towards power-aware and thermal-aware scheduling.

References

[1] Iyenger, V., Chakrabatry, K.: System-on-a-Chip Test Scheduling With Precedence
Relationships, Preemption and Power Constraints. IEEE Trans. on Computer-
aided Design of Integrated Circuit and Systems 21(9), 1088-1094 (2002)
[2] Cota, E., Liu, C.: Constrain-Driven Test scheduling for NoC-Based Systems. IEEE
Trans. on Computer-Aided Design of Integrated Circuit and Systems 25(11),
2465-2478 (2006)
[3] Manna, K., Khaitan, P., Chattopadhyay, S., Sengupta, I.: Particle Swarm Opti-
mization based Technique for Network-on-Chip Testing. In: Proceedings of IEEE
Intl. Conf. EAIT, pp. 66-69 (2012)
[4] Iyengar, V., Chakrabarty, K.: Test wrapper and test access mechanism co-
optimization for system-on-chip. Journal of Electronic Testing: Theory and
Appl. 18, 213-230 (2002)
[5] Marinissen, E.J., Iyengar, V., Chakrabarty, K.: A Set of Benchmarks for Modular
Testing of SOCs. In: Proceedings of International Test Conference, pp. 519-528
(2002)