Kapees: A New Tool for Standard Cell Placement - VLSI Design and Test - page 71

Fig. 2. Method 2 for Perturbation

because the estimates for bin width separation are not correct. We do not aim to
obtain a balance for bin widths but only for row widths. In the second method
the wire length during cell swapping stage correlates well with spread out cost.

3.3 Greedy Cell Swapping

In this stage, initially, all the cells for the bins are spread out. Then we randomly
pick two cells in suciently close vicinity and see if swapping their coordinates
with each other can reduce the wire length. The swapping is done in such a way
that there does not exist any overlap between the adjacent cells. All the cells to
the right of the selected cells are spread out.

Tabl e 1. Characteristics of IBM version 2 benchmarks

Circuits Cell Count Net Count Rows core utilization

IBM01 easy 12028 11753 132 85.12%

IBM01 hard 12028 11753 130 88.00%

IBM02 easy 19062 18688 153 90.42%

IBM02 hard 19062 18688 149 95.28%

IBM07 easy 44811 44681 233 89.95%

IBM07 hard 44811 44681 226 95.30%

IBM08 easy 50672 48230 243 90.03%

IBM08 hard 50672 48230 236 95.16%

IBM09 easy 51382 50678 246 90.24%

IBM09 hard 51382 50678 240 95.12%

IBM10 easy 66762 64971 321 90.22%

IBM10 hard 66762 64971 313 95.08%

IBM11 easy 68046 67422 281 90.11%

IBM11 hard 68046 67422 273 95.33%

4 Experimental Results and Conclusion

We selected the IBM version 2.0 benchmarks to test our tool. These benchmarks
have cell counts ranging from 12028 to 68046. Most of the current state of art