10 Gbps Current Mode Logic I/O Buffer - VLSI Design and Test - page 65

At the off-chip load, an eye diagram is simulated using a pseudo-random bit
sequence (2 5 -1) as input. Figure 6 shows the eye diagram obtained. Peak to peak jitter
is calculated to be 4.95 ps, and an eye opening of ±125 mV which is quite acceptable
for the OC-192 application.

6 Conclusion

A new high-speed CMOS buffer is proposed that can work at up to 10 Gbps, without
the need of an inductive peaking architecture, thus saving on valuable chip area. The
power consumption is comparable to previously reported work [7].

References

1. Heydari, P., Mohanavelu, R.: Design of Ultrahigh -Speed Low Voltage CMOS CML
Buffers and Latches. IEEE Trans. VLSI Syst. 12, 1081-1093 (2004)
2. Razavi, B.: Design of Analog CMOS Integrated Circuits. McGraw-Hill, New York (2001)
3. Green, M.M., Singh, U.: Design of CMOS CML circuits for high speed broadband
communications. In: Proc. Int. Symp. Circuits and Systems, pp. II-204-II-207 (2003)
4. Tsuchiya, A., Kuboki, T., Onodera, H.: Low -Power Design of CML Drivers for On Chip
Transmission Lines. IEICE Trans. Electron. E90-C, 1274-1281 (2007)
5. MOSIS Integrated Circuit Fabrication Service, http://www.mosis.org
6. Maxim Corporation, 'MAX3804 I/O model 10Gbps equalizer' (2008),
http://www.maximic.com/tools/spice/fiber/app_3804ete.pdf
7. Galal, S., Razavi, B.: 10 Gb/s Limiting amplifier and laser/modulator driver in 0.18 ʼ m
CMOS technology. IEEE J. Solid-State Circuits 38, 2138-2146 (2003)