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10 Gbps Current Mode Logic I/O Buffer
Akhil Rathore 1 and Chetan D. Parikh 2
1 Dhirubhai Ambani Institue of Information and Communication Technology,
Gandhinagar, India
2 Institute of ICT, Ahmedabad University, Ahmedabad, India
chetan.parikh@ahduni.edu.in
Abstract. A new architecture for a high speed CML buffer is presented. The
buffer is designed for OC-192/STM-64 applications to be used in the limiting
amplifier which is a critical block in optical communication systems. OC-
192/STM-64 works around 10Gbps. The proposed architecture is also more
efficient in terms of area.
1
Introduction
In high speed serial links and optical communication, buffers create a bottleneck. In
such systems, Current- mode logic (CML) buffers [1] are commonly used. Using
current as the signaling variable rather than voltage, allows for low voltage
swings between the high and low digital levels. Systematic design procedures for
CML buffers have been reported by Heydari and Mohanvelu [1] and by Green and
Singh [3]. In conventional CML buffers inductive peaking [1] is used to enhance
bandwidth but it requires monolithic inductors, which needs a large silicon area.
Current architectures of output buffers use f T doublers and inductive peaking together
and can obtain data rates of up to 10 Gbps, but these also require a large silicon area
[3]. The conventional CML buffer suffers from the Miller effect which degrades high
frequency operation.
This paper presents a new architecture which avoids miller effect and works around
10 Gbps in a 0.18
m CMOS technology. It requires less chip area and power than
existing architectures. The contents of the paper are as follows: Section 2 describes the
conventional CML buffer, its operation and its limitations at high frequencies.
Sections 3 and 4 describe the proposed architecture, its working and the various design
issues. In section 5 simulation results are shown and section 6 concludes this paper.
μ
2
CML Buffer
This section describes the basics of a conventional CML buffer, its advantages,
and its limitations at high frequencies. The various design issues related to a CML
buffer are discussed in [1, 3, 4].
 
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