Information Technology Reference
In-Depth Information
Tabl e 3.
Comparison with previous designs in 180nm and 90nm CMOS
Design
Area in 180nm
(
μm
2
)
Area in 90nm
(
μm
2
)
Min.delay(ps) Max.delay(ps)
Proposed 3,728.5
2,041.87
13
3900
MVDL[4] 14,441
5,979.6
14
900
OCDM[6] 4,849
2,918.44
7
805
To measure delay difference between all type of signals, whether falling or rising,
a DG gate used in [5], is incorporated in the proposed design.
5Con lu on
In this paper a delay measurement architecture for path delay characterization
has been proposed. A new delay mechanism is employed in which the signal
transition that occurs earlier is delayed more in each delay stage irrespective of
whether the signal travels through upper or lower delay chain. Stages with high
delay range are used to reduce the number of stages and increase the measure-
ment range, without affecting the resolution of measurement which depends on
the delay range after second crossover. This makes it possible to detect a small
path delay as well as very large path delay using same architecture. Simulation
results on C880 benchmark circuit validates effectiveness of the proposed on-chip
path delay measurement architecture.
References
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2. Zhang, Y., Yu, H., Xu, Q.: Coda: A concurrent online delay measurement archi-
tecture for critical paths. In: 2012 17th Asia and South Pacific Design Automation
Conference (ASP-DAC), January 30-Feburary 2, pp. 169-174 (2012)
3. Yotsuyanagi, H., Makimoto, H., Hashizume, M.: A boundary scan circuit with time-
to-digital converter for delay testing. In: 2011 20th Asian Test Symposium (ATS),
pp. 539-544 (November 2011)
4. Datta, R., Sebastine, A., Raghunathan, A., Carpenter, G., Nowka,
K., Abraham, J.A.: On-chip delay measurement based response analy-
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27-May 1, pp. 249-254 (2008)
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