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3.2 Detect Block
Detect block is designed to detect a condition in which the output of DFF in
a preceding stage is a rising one and the next stage DFF output remains zero.
To implement this, two positive level sensitive latch are used to form one Detect
block. Figure 8 , shows two such adjacent Detect blocks. Qi represents DFF
output of i th stage, where i
[3 ,N ] in a N stage measurement architecture. The
first latch in a Detect block is initially reset to '0' with a '1' at its data input and
Qi connected to its clock input. The second latch is initially set to '1' with Q(i+1)
connected to its data input. The output of first latch triggers second latch. The
output of the second latch is called Detect(Dt) and the inverted form of Dt is
called Detectbar(Dtbar). Once a Dt in any preceding Detect block becomes '0',
the second latch of the subsequent Detect Block's should be triggered irrespective
of the output of first latch. This is implemented by using Dtbar(i) signal and an
'OR' gate.
āˆˆ
Qi
Q(i+1)
1
1
set
reset
set
reset
Dtbar(i+1)
Qi
Q(iāˆ’1)
Dtbar(i)
Previous stage Detectbar
OR
Zero if there is no preceding detect block
Detect Block
Fig. 8. Two adjacent Detect Blocks each containing two positive level sensitive latch
All type of possible sequences of a DFF output at the input of Detect block
is shown in the Table 1 . The output of DFF rises to a one from initial value of
zero, which is represented by R in Table 1 . When Dt becomes zero, a second
crossover is said to have taken place.
4 Experimental Results
The proposed architecture is integrated with the C880 benchmark circuit [9],
using a delay measurement scheme employed in [6]. This integrated architecture
was simulated in SPICE using TSMC 180nm CMOS process to validate the
working of proposed approach. The transition pattern is generated using KF-
ATPG tool. The details of this tool is described in [8]. Transitions are generated
on four different paths of C880 benchmark circuit. The output stored in the DFF
is shifted out serially using a clock SCLK with a period of 1ns. Figure 9 shows
the serially shifted data after the completion of measurement. Values of N1,N2
and N3 can be found from Figure 9 and then path delay can be calculated using
(3). The path delay measured across these paths is shown in Table 2 . Path
delay column is subdivided into Using Arch. column which shows the path delay
measured using proposed architecture and simulation column which shows the
path delay measured using SPICE simulation.
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