An Area Efficient Wide Range On-Chip Delay Measurement Architecture - VLSI Design and Test - page 53

Stage(N1+N2+N3)

Stage(N1+N2+N3+1)

START(N1+N2+N3)

Q=0

START(N1+N2+N3+1)

Q=1

t1+N1*D1−N2*D2+(N3−1)*D3 Third Crossover

t1+N1*D1−N2*D2+N3*D3

STOP(N1+N2+N3)

STOP(N1+N2+N3+1)

t2 t2

Fig. 5. Time relationship between the input signals in the third crossover stage and
its preceding stage

N 1 ≤

( t 2 − t 1) ≤ N 1 × D 1 − ( N 2 × D 2) + ( N 3 × D 3)

× D 1 −

( N 2

× D 2) + (( N 3 − × D 3)

1)

(3)

≤

( N

− × D 1

Max.Path Delay 1) (4)

First crossover Third crossover

Second crossover

N2 ones before
Second Crossover

N1 zeroes before
First Crossover

N3 zeroes before
Third Crossover

Fig. 6. General form of output containing sequence of ones and zeroes

Data stored in all the DFF, forms a sequence of zeroes and ones as shown
in the Figure 6 . N1, N2 and N3 in Figure 6 , represents the count of these
zeroes and ones. Delay is measured by observing this sequence which is shifted
to output by connecting DFF of all the stages in the form of shift register.

3 Implementation Details

The proper working of the architecture lies in its ability to change the delay
range when a crossover takes place. It must differentiate between the initial
output of DFF and output of DFF after second crossover. This section gives
implementation details of the proposed delay measurement architecture.