Information Technology Reference
In-Depth Information
3.2 Architecture 2 (A2)
This architecture is described in Bluespec SystemVerilog[7]. Bluespec allows de-
signs to be described in terms of rules or internal behaviors and transactions
with other modules through interfaces.
This architecture, unlike A1, uses an elastic pipeline. An elastic pipeline is
based on the Producer-Consumer model. In this model, whenever a consumer
block is ready to accept new data, it asks the producer it is associated with to
feed it, provided it can. This is in contrast to A1, where the control is centralized.
This producer-consumer model allows for easy replacement and modification of
modules without changing the other blocks, as long as the replacement module
provides the same interface.
The pipeline structure is implemented using First in First out (FIFO). FIFOs
allow for communication between blocks using enqueue (enq) and dequeue (deq)
operations. These methods are guarded; i.e., an enq operation can occur only
if the FIFO can accept the new data and a deq operation can happen only if
the FIFO is not empty. Hence, for each stage to have a one clock latency, a
2-element FIFO is needed or a 1-element FIFO which can simultaneously enq
and deq on empty is needed. The latter has a combinational path from the
input to the output and also consumes less area and power. The combinational
path translates to a reduction in the maximum frequency of operation. But, this
reduction in the clock frequency was a non-issue as the timing requirements were
easily met.
As previously hinted, the front-end controller does not perform heavy duty
tasks such as controlling the dataflow in A2. It does specifies/tags the end of
frame bit. It also specifies the scrambler seed. It also specifies whether BCH
encoding is done or not. This scheme is employed by HARQ mechanism.
The design of the PHR block is also different. To make sure that no bubbles
were present at the overall output, the PHR stream must be immediately fol-
lowed by the payload without bubbles in between. Bubbles are essentially caused
by the use of shortened BCH code, which drops bits from the BCH coder it is
derived from. To prevent bubbles, the entire word was computed and stored in
a register the size of the PHR, in architecture A1. To achieve a reduction in
the register count, partial computation of the PHR was employed in A2. A 25-
element FIFO was used. This allowed for computations to happen partially. As
soon as the PHR FIFO starts draining, new values are computed. Initially, these
are the values to be dropped, which are not enqueued. During the last value
that is dequeued, the data to be present is calculated and added to the FIFO.
Thus, the bubbles in the pipeline are avoided at a reduced cost in power and
area when compared to A1.
4 Results and Discussion
The performance characteristics of both the architectures are tabulated below.
These characteristics are for the 0.13
μ
m CMOS technology, operating at a
supply voltage of 1.08 V with clock frequency of 487.5 kHz. The Bluespec code
