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Counter=0,N=63,K=51,Scount=0
datalength=length of MPDU
length=length+1
length=length-1
counter=counter+1
Scount=Scount+1
YES
NO
control==1
control=0
NO
Counter==192
YES
NO
Scount==K
brem =
K-Scount
size=N-Scount
YES
Scount=Scount+1
YES
b rem
0
control=1
brem =0
NO
Counter=0
NO
Scount==N
NO
YES
length
3K
YES
Scount=0
NO
YES
length
2K
NO
YES
NO
Scount
K
length
K
YES
NO
NO
Scount
60
NO
Scount
K
length-b rem
2K
NO
Scount
K
YES
YES
intr size =
3N+size
NO
length
brem
YES
length-b rem
YES
N bs =
3K-length
NO
K
YES
YES
intr size =
3N+size
intr size =
size
intr size =
3N+size
N bs =
2K+b rem -length
N bs =
b rem -length
N bs =
2K+b rem -length
Fig. 3. Flowchart of transmitter controller of A1
The Scount is a mod-63 counter that sets contol to '1' when Scount is greater than
51. When contol=1 , the output of the scrambler is stalled, while the BCH encoder
outputs the parity bits. The intr size represents the size of the last interleaving
block and n bs represents number of bits to be stuffed in the last BCH block.
The interleaver consists of two banks, each a 192 bit register. At any given
instance, one of the banks will act as the input bank and the other will act as
the output bank. The input bank will take the input from the BCH coder, while
the output is taken from the other bank. The input bank will be fully filled and
the output bank will be fully drained at the same instance, and the roles will be
reversed. The address is generated internally with information about the block
size from the controller. The PHR frame is initially processed and then stored
in a 40-bit register. The controller generates a PHR enable signal, which when
active, pipes the output from the PHR register to the output. Once finished, the
PSDU is provided to the next stage.
 
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