Information Technology Reference
In-Depth Information
Further analysis can establish better correlation between actual faults and their
surrogates.
References
1. ATPG and Failure Diagnosis Tools. Mentor Graphics Corp., Wilsonville, OR (2009)
2. Python Tutorial Release 2.6.3. docs@python.org. Python Software Foundation
(2009)
3. Abramovici, M., Breuer, M.A.: Fault Diagnosis Based on Effect-Cause Analysis:
An Introduction. In: Proc. 17th Design Automation Conf., pp. 69-76 (June 1980)
4. Abramovici, M., Breuer, M.A.: Multiple Fault Diagnosis in Combinational Circuits
Based on an Effect-Cause Analysis. IEEE Transactions on Computers C-29(6),
451-460 (1980)
5. Agrawal, V.D., Baik, D.H., Kim, Y.C., Saluja, K.K.: Exclusive Test and Its Ap-
plications to Fault Diagnosis. In: Proc. 16th International Conf. VLSI Design,
pp. 143-148 (2003)
6. Alagappan, C.: Dictionary-Less Defect Diagnosis as Real or Surrogate Single Stuck-
At Faults. Master's thesis, Auburn University, Auburn, Alabama (May 2013)
7. Beckler, M., Blanton, R.D.(S.): On-Chip Diagnosis for Early-Life and Wear-Out
Failures. In: Proc. International Test. Conf., pp. 1-10 (November 2012)
8. Bushnell, M.L., Agrawal, V.D.: Essentials of Electronic Testing for Digital, Memory
and Mixed-Signal VLSI Circuits. Springer, Boston (2000)
9. Cox, H., Rajski, J.: A Method of Fault Analysis for Test Generation and Fault
Diagnosis. IEEE Trans. Computer-Aided Design of Integrated Circuits and Sys-
tems 7(7), 813-833 (1988)
10. Grimaila, M.R., Lee, S., Dworak, J., Butler, K.M., Stewart, B., Houchins, B.,
Mathur, V., Park, J., Wang, L.-C., Mercer, M.R.: REDO - Random Excitation and
Deterministic Observation - First Commercial Experiment. In: Proc. 17th IEEE
VLSI Test Symp., pp. 268-274 (April 1999)
11. Kofler, M.: Definitive Guide to Excel VBA. Apress, New York (2000)
12. Millman, S.D., McCluskey, E.J., Acken, J.M.: Diagnosing CMOS Bridging Faults
With Stuck-At Fault Dictionaries. In: Proc. International Test. Conf., pp. 860-870
(September 1990)
13. Reddy, S.M., Pomeranz, I., Kajihara, S.: On the Effects of Test Compaction on
Defect Coverage. In: Proc. 14th IEEE VLSI Test Symp., pp. 430-435 (April 1996)
14. Stroud, C.E.: A Designer's Guide to Built-in Self-Test. Springer, Boston (2002)
15. Venkataraman, S., Drummonds, S.B.: POIROT: A Logic Fault Diagnosis Tool and
Its Applications. In: Proc. International Test Conf., pp. 253-262 (2000)
16. Wang, L.C., Williams, T.W., Mercer, M.R.: On Eciently and Reliably Achieving
Low Defective Part Levels. In: Proc. International Test Conf., pp. 616-625 (October
1995)
17. Zhang, Y., Agrawal, V.D.: An Algorithm for Diagnostic Fault Simulation. In: Proc.
11th Latin-American Test Workshop (LATW), pp. 1-5 (March 2010)