Information Technology Reference
In-Depth Information
Tabl e 4.
Multiple (two) fault diagnosis with 2-detect tests
Circuit No. of DC % of cases diagnosed CPU* Fault ratio
name patterns (%) Both faults One fault No fault s SET1 SET2
C499 3872 98.400 49.056 20.754 30.188 0.696 0.371 11.555
C1908 6425 86.203 90.566 0.000 9.433 2.314 0.488 7.232
C7552 27756 86.750 96.226 1.886 1.886 17.291 0.358 5.905
∗
PC with Intel Core-2 duo 3.06GHz processor and 4GB memory
Tabl e 5.
Single fault diagnosis with diagnostic patterns
Circuit No. of No. of DC Diagnosis CPU* Fault ratio
name outputs patterns %
%
s
SET1 SET2
C17
2
12
100
100
0.067 1.000 1.780
∗
PC with Intel Core-2 duo 3.06GHz processor and 4GB memory
the inputs of the XOR gate, but also for any case where fault effects are being
propagated through an XOR gate. The situation will improve while considering
more than two faults to be present in the circuit because the probability of a
complete circular masking decreases with the increase in the number of faults.
In circuit C499, the presence of this huge XOR tree increases circular masking
and thereby deteriorates the performance of the diagnosis algorithm. But as
discussed before, the algorithm does produce reasonable results even in a highly
pessimistic environment, where choices (close neighborhood faults selected) are
made in such a way that the probability of masking is high. One other ISCAS'85
benchmark circuit, which has (2-input) XOR gates present, is circuit C432. But
it has only 18 XOR gates, which do not form a tree and hence the diagnostic
percentage is not hurt significantly.
The ratio of faults in SET1 in Table 3 is less than 1 because in most cases,
faults reported in SET1 include one of the actual faults, its equivalent faults
and the opposite polarity faults. The other actual fault, its equivalent faults
and opposite polarity faults are present in SET2. Hence, the resolution of SET1
faults is mostly closer to 0.5 than being 1.0 when we consider two faults.
The same three circuits show a comparatively poorer SET2 resolution. Hence,
2-detect patterns are used to show that the diagnostic resolution improves upon
improving the diagnostic coverage of the test pattern set. The results of this
experiment are shown in Table 4. Once again it is seen that, for small increase
in diagnostic coverage (
DC
) of the patterns by 1.016% (maximum) for circuit
C1908 the resolution is improved by almost 40%. Other two circuits show a
similar trend.
The last experiment was to try the diagnosis procedure on a 100% diagnostic
test pattern set. The circuit C17 reports 95.454% of diagnostic coverage (
DC
)
with as few as 5 patterns that have 100% detection coverage. The total number
of faults in the circuit is 22. There was only one fault pair that was not distin-
guished. Adding one more pattern that distinguishes the fault pair yielded 100%
diagnostic coverage as expected. The diagnostic algorithm was then run using
this test pattern set to yield the results shown in Tables 5 and 6.
