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c1355 the simulation time is improved. Since in the case of earlier work the ILP
problem is formulated for entire circuit which causes around 690 variables and
11K of constraints to be dealt with where as for the level based approach the
ILP is formulated for each level and are solved independently in which case only
194 variables and 9K constraints are involved. The estimated toggle activity by
proposed method is less than that of the earlier method. For circuits from c432
to c2670 the estimated toggle activity is significantly better.
The c499 and c1355 are both error correction and translation(ECAT) circuits.
The % of toggle activity for these circuits are low compared to rest of the circuits
because the ECAT circuit consists of xor tree with re-convergent fanout. The %
of toggle indicates that i) if it is 100% then the solver has found the solution,
ii) if it is less than 100% and solver run time reaches it's time out limit than
the solution is approximate, iii)if the solver finishes before time out than the
solution reached the maximum achievable toggle activity.
Tabl e 2.
Comparison of estimated toggles and simulation time
Proposed Methodology [10]
Ckt #PIs #Ckt #MaxLevel EstToggle %Toggle SimTime EstToggle SimTime
Nets
Nets
in sec.
in sec.
c01
4
9
4
4
100
0.04
9
0.01
c04
1
4
3
3
100
0.02
4
0.09
c05
3
8
3
3
100
0.03
7
0.05
c11
4
6
4
4
100
0.03
5
0.02
c14
2
4
2
2
100
0.03
3
0.03
c17
5
6
2
2
100
0.04
6
0.02
c432
36
296
27
27
100
9.25
243
8.86
c499
41
626
194
76
39.17
34.45
360
3406.00
c880
60
592
58
58
100
22.34
491
21.55
c1355 41
690
194
76
39.17
44.92
415
3616.48
c1908 33
1291
92
92
100
269.2
832
2371.53
c2670 233 1925
147
144
97.95
545.7
1362
559.65
7 Conclusion and Future Work
In the proposed method peak power estimation in terms of toggle activity count
using level based approach is explored. The proposed method generates input
vector pair which maximizes the toggle activity for a level. Through experimen-
tal results and theoretical analysis we have demonstrated that the level based
approach is better than whole circuit approach. The CPLEX solver runs 10 to
50 time faster for this approach than the whole circuit approach.
Extending the work to sequential circuit is a practical necessary and challenge.
Consideration of variable delay model along with fanout load could make the
estimation realistic. Hence we set forth the above as next step of this work.
