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Hence the modified objective function can be expressed mathematically as
follows.
Formulation of Level-objective Function:
Maximize
j,i
x
j.i
toggle
(4)
where
j
varies from 1 to L where L is the total number of levels and
i
varies
from 1 to n where
n
is total number of nets in a particular level.
Constraint Set:
All the three constraints, I/O constraints, linearization constraints, and toggle
constraints(refer to Section 4), are defined only for that part of the circuit which
is currently in active state which mean that gates from Level-1 to Level-j are
considered and rest are ignored.
5.1 Computation of Maximum Peak Activity
Now we are all set to compute the maximum peak activity using
level-BILP
formula. The peak power is expressed as Eqn-2. More precisely, the final peak
activity is the maximum among the peak activity at each level. Hence by itera-
tive execution of
level-BILP
for every level the level peak activity,
A
l
in Eqn-2,
can be computed. In programing structure this can be written in following way.
for
l
=1toL
A
[
l
]=
Maximize
l,i
x
l.i
toggle
Now the peak power will be computed using Eqn-2 as
P
peak
=
Max
(
A
[
l
]).
6 Evaluation on ISCAS-85 Circuits
To evaluate the accuracy and eciency of the proposed estimation methodology,
we have experimented on ISACS-85 circuits set. We have solved the binary inte-
ger linear program(BILP) using CPLEX ILP solver[8]. CPLEX solver is found
to be faster for BILP problem[3]. The benchmark circuits are standardised to
one-input and two-input gates.
The experimental results are shown in Table 2. Complexity of the circuit is
reported in 2nd and 3rd columns,column #PI indicates the number of primary
inputs and #Ckt Nets indicates the total number of nets in circuit. The 4th, 5th,
and 6th columns reports the activity count. The column #MaxLevelNet indicates
the maximum number of nets over the levels, column EstToggle indicates the
estimated toggle using proposed method, and columns %Toggle reports the %
of estimated toggle activity over #MaxLevel Nets. The last two columns are
results from the previous work by the authors [10].
For all the circuits the CPLEX Solver could solve in no more than 546 second
which is around 7 time faster than the worst time in [10]. For circuit c499 and
