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methodologies were proposed in [11] for determining lower and upper bounds on
maximum power dissipation. To calculate the lower bound, the authors have
proposed an ATPG based technique; while for upper bound they have pro-
posed a monte-carlo based simulation technique. An improved version, based
on D-Algorithm, of this technique is proposed in [1]. Genetic Algorithm based
approach is examined by Hsiao et al[2].
M Pedram and Q Wu et al. have explored probabilistic based ideas [12][13].
Q Wu et al.[13] have proposed a technique based on limiting distribution of
extreme order statistics. The challenge in this approach is to show with higher
confidence level that the estimated power is indeed the real power. As stated
earlier such kind of techniques are time ecient. However diculty is there in
accuracy. More detailed survey of the earlier techniques are carried out by Farid
N. Najm[14] and M Pedram[4].
Keeping accuracy and eciency in forefront in this work we have proposed a
level-accurate peak activity estimation methodology. Experimental results show
the improvement in accuracy and eciency.
3 Level-Accurate Power Estimation: Methodology
As it is discussed in Section 2, all the power estimation techniques, particularly
the peak power estimation techniques, proposed so far perform estimation of the
peak power considering the nodes from entire circuit. Such approach leads to
pessimistic results because all the circuit nodes does not switch simultaneously.
Even though different delay models, zero delay, unit delay, type-1 variable delay,
and type-2 variable delay models[2], are taken in to consideration to capture
the spurious activity like glitches and hazards this leads to pessimistic value
since the toggles are accounted from entire circuit. Our observation is that, since
technology is shrinking towards nano meter geometry it is sucient to estimate
the worst case peak activity in a particular level to capture the information on
IR-drop, ground bounce, and associated delays.
The proposed level-accurate method is demonstrated in following sections.
3.1 Leveling of the Circuit
The different levels of the circuit is determined by assigning the level number
at each net. The assignment of level number is performed on per gate basis. For
each gate the level number of output net is determined based on the current
levels of input nets by following simple formula.
L out = Max ( L in 1 ,L in 2 , ... )+1
(1)
where L out is the level number of output net of i th gate, L in 1 is the level number
of input net-1 of i th gate.
In figure Fig-1 the leveling of each gates along with output net is shown as
Level-1, Level-2, and Level-3. For example, for the circuit in Fig-1 the level
number of output nets of gate-1.1(XOR gate) and gate-1.2(NAND gate) is 1,
 
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