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Level-Accurate Peak Activity Estimation
in Combinational Circuit Using BILP
Jaynarayan T. Tudu
1
, Deepak Malani
2
, and Virendra Singh
2
1
Computer Science and Automation, Indian Institute of Science, Bangalore
jayttudu@csa.iisc.ernet.in
2
Electrical Engineering, Indian Institute of Technology, Bombay
malani@ieee.org, viren@computer.org
Abstract.
Due to shrinking size of transistor and increasing circuit
complexity the instantaneous power became a concern for circuit reli-
ability. Higher IR-drop/Ground bounce induces unpredictable delay and
can cause soft error. Higher
V
dd
can cause thermal hot-spot. Appropri-
ate selection of
V
dd
and design of power distribution network(PDN) plays
crucial role in alleviating such issues. The design of an ecient PDN en-
tirely depend on the knowledge of power budget and dynamic behaviour
of instantaneous activity.
In this work we have proposed an ecient and level-accurate instanta-
neous peak activity estimation method. The proposed work uses binary
integer linear programming technique(BILP). The methodology perform
to estimate the peak activity and generate corresponding input vec-
tor pair. The experimental results on ISCAS-85 circuit reveals that the
level based approach is 10 to 50 time faster than approach based on
total-circuit-ILP formulation. The estimated peak activity is 4 to 9 time
improved than previous approach.
Keywords:
Peak power estimation, Combinational circuits, Integer
Linear Programming.
1 Introduction
In todays System-on-chip (SoC) designs, the amount of logic per unit area is very
high. Coupled with fast clock rates, the switching power has been on the rise.
High power dissipation in certain areas of a chip leads to formation of thermal
hot-spots and also impact the reliability of the chip. Besides, high current de-
mand during switching stresses local power grid. This effect is addressed during
the design of power delivery network (PDN). Decoupling capacitors are inserted
to account for surge demand in current. This solution prevents supply voltage
droop from falling below permissible limits, to avoid delay faults.
All these factors mentioned above, need proper estimation of average and
peak power demand in a chip. Power grid design can be effective with local ob-
servability, especially during peak switching activity. However, the estimation
practices are either probabilistic (considering average activity factor) or insuf-
ficient (simulation based). This is accounted for by keeping excessive margins
