3D CORDIC Algorithm Based Cartesian to Spherical Coordinate Converter - VLSI Design and Test - page 343

processing whereas when it is 1, it sends Z and one of the intermediate output of
CORDIC pipeline recursively for processing.
Enable signal also acts as a control so that output data from output register is
available after every two clock cycle. Basic CORDIC pipeline is responsible for the
rotation of the vector in single direction and computes its new value after each
iteration using simple shift and add operation as per the CORDIC equation.

5 FPGA Implementation and Results

Functional simulation and Hardware implementation of the proposed Converter for
FPA and HRPA is carried out in Xilinx ISE9.2i on Virtex-5 pro device using Verilog.
Summary of hardware used is given in Table 1.

Table 1. Hardware Summary for 16 Bits Wordlength Implementation

Parameter Fully Pipeline Architecture Recursive
Architecture
Flipflops 959 462
LUTs 2939 1482
IOB 101 66
BUFG 1 1
Maximum Freq 95.786 MHz 42.28 MHz
It is evident from the results that hardware utilization of recursive architecture
HRPA is less as compared to the fully pipelined FPA. But the Maximum operation
frequency of FPA is better than HRPA. The output data rate is one set of data for each
clock cycle for FPA whereas it is one set of data for two clock cycle for HRPA.
Error analysis of the results revealed that for 16 bit word length minimum Bit Error
Position (BEP) is 12 for both the architectures. This implies that out of 16 bits
minimum 12 bits are error free which is sufficient for all practical purposes as per
[11]. The BEP for spherical angles θ and Φ are plotted in Fig. 3.

Fig. 3. Bit Error Position (BEP) for Spherical Coordinates θ and ʦ