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Two types of architecture i.e. Fully Pipelined and Hybrid Recursive pipelined
architecture are proposed for hardware implementation of the Converter. Both
architectures are compared for their performance in terms of speed and area.
Mathematical verification and error analysis is also carried out for both the designs.
This paper is structured as follows: Section 2 explains the overview of CORDIC
algorithm; Section 3 details the steps of proposed scaling free 3D CORDIC algorithm;
two different architectures are suggested in Section 4; Section 5 details the FPGA
Implementation and results with Section 6 summarizing the conclusions; references
are listed in Section 7.
2
CORDIC Algorithm Overview
CORDIC Algorithm is based on Givens rotation of vectors in 2D space using simple
shift and add operations. CORDIC Algorithm can operate in two modes namely:
rotation and vectoring. In rotation mode, the objective is to rotate a vector through a
given angle using series of iteration and to reduce the residual angle to zero after each
iteration. Sine and Cosine of given angle can be computed using these iterative
rotations.
In vectoring mode, the magnitude and the phase of given vector is computed by
rotating a vector iteratively with the aim to align it with x axis. The trajectory of
rotation for both the modes can be linear, circular or hyperbolic depending upon the
requirement.
2.1
Conventional CORDIC Algorithm
The conventional CORDIC algorithm [6] is derived from general equation of vector
rotation. If a vector V with components (Xi, Yi) is iteratively rotated through an angle
ʱi, a new vector V' with components (Xi+1, Yi+1) is formed.
In matrix form, the value of vector after this micro rotation can be represented as:
1
d
·tan
·
.
(1)
·
d
·tan
1
where
cos
and
2
The sign sequence d
i
Є{1,-1} is so selected that:
(2)
·
Where, 'w' is the word-length in bits.
