Information Technology Reference
In-Depth Information
Lemma 3.
Insertion of
G
1
,
G
2
,
G
3
, and
G
4
for a gate G causes the same pattern to
appear at the input of G and output of
G
4
when
C
1
=1,
C
2
=0.
Proof.
m
= input to target of
G
G
1
produces at
C
2
:
m
↕
C
2
=
m
↕
0=
m
M
where
M
=
m
, when target flips the bit
=
m
, when target does not flip the bit
G
3
produces at target line :
M ↕ C
1
.C
2
=
M ↕
G
2
produces at
C
2
:
m
↕
1.
C
2
=
M ↕ m ↕ M
=
m
Thus in the Target line the output is restored the input value after
G
3
G
4
produces at
C
2
:
C
2
↕
x
i
1
.x
i
1
.....x
i
l
=
m
↕
M
↕
x
i
1
.x
i
1
.....x
i
l
(1)
M
=
m
,
x
i
1
.x
i
1
.....x
i
l
=1
=
m
,when
x
i
1
.x
i
1
.....x
i
l
=0
Thus at line
C
2
, we get either
m
m
↕
↕
1or
m
↕
m
↕
0
In either case the value is 0
C
2
is restored to its original value after
G
4
.
In line
C
1
, there is no target thus the value is always retained.
Therefore it is possible to restore the same test pattern at the output level.
Lemma 4.
Insertion of
G
1
,
G
2
,
G
3
,
G
4
, and
G
5
for a gate G causes the same pattern
to appear at the input of G and output of
G
5
when
C
1
=1,
C
2
=0.
Proof.
m
= input to target of
G
Since the
G
1
,
G
2
and
G
3
is same as
G
1
,
G
2
and
G
3
their output is also same.
G
4
produces at
C
2
:
C
2
↕
x
i
1
.x
i
1
.....x
i
l
=
m
↕
M
↕
x
i
1
.x
i
1
.....x
i
l
(1)
M
=
m
,
x
i
1
.x
i
1
.....x
i
l
=0
=
m
,when
x
i
1
.x
i
1
.....x
i
l
=1
Thus at line
C
2
, we get either
m
m
↕
↕
0or
m
↕
m
↕
1 ....(2)
G
5
produces at
C
2
:
C
2
↕
m
↕
C
1
=
C
2
↕
1=
m
↕
0
↕
1 or
m
↕
m
↕
1
↕
1
=0
In either case the value is 0
C
2
is restored to its original value after
G
4
.
In line
C
1
, there is no target thus the value is always retained.
Therefore it is possible to restore the same test pattern at the output level.
Theorem 1.
The modified circuit derived by the proposed DFT method admits the
following universal test set of length
(
n
+2)
.
⊛
⊞
x
1
x
2
···
x
n
C
1
C
2
⊝
⊠
01
···
110
10
···
110
.
.
.
.
.
.
.
.
S
U
=
11
···
010
00
···
001
00
···
000
