Information Technology Reference
In-Depth Information
In our DFT design, we are using two additional input lines
C
1
and
C
2
. For each gate
G
, some additional gates are introduced to maintain the same test set
T
to be applied to
thenextgateof
G
. We may skip the insertion of additional circuitry when
G
is the last
gate in the original circuit. There may be three cases when
G
is not the last gate.
Case 1: The number of control lines (
l
)=0
G
is duplicated in the same way as in [4]
Example 1
: Consider the gate
G
2
in Fig. 4. In its DFT design in Fig. 5,
G
2
has been
duplicated with an additional control on line
C
1
.
Case 2:
l
, where n is the size of the original circuit.
For any gate
G
(
TOF
(
C,T
)) of Fig. 3(a) with control in the original circuit we are in-
serting a set of 4
k
-CNOT gates
TOF
(
T,C
2
) as
G
1
,
TOF
(
T,C
2
) as
G
2
,
TOF
(
C
1
,C
2
,
T
) as
G
3
and
TOF
(
C,C
2
) as
G
4
, as shown in Fig. 3(b).
=0and
Con
(
G
)
≤
n/
2
Fig. 3.
Testing of gate
G
in the proposed DFT design
Example 2
:
G
3
and
G
4
of Fig. 4 are the examples of such case. The set of additional
4 gates for these gates is shown in Fig. 5.
Case 3:
l
.
For any gate
G
(
TOF
(
C,T
)) of Fig. 3(a) with control in the original circuit we are in-
serting a set of 5
k
-CNOT gates
TOF
(
T,C
2
) as
G
1
,
TOF
(
T,C
2
) as
G
2
,
TOF
(
C
1
,C
2
,
T
) as
G
3
,
TOF
(
n
=0and
Con
(
G
)
>
n/
2
C,C
2
) as
G
4
,and
TOF
(
C
1
,C
2
) as
G
5
as shown in Fig. 3(c) .
Example 3
:
G
1
of Fig. 4 is the examples of case 3. The set of additional 5 gates for
this gate is shown in Fig. 5.
−
Fig. 4.
A reversible circuit
This procedure is well described in the algorithm DFT that adopts 3 approaches in
dealing with addition of extra circuitry to undo the change made by a gate so that the
same universal test set can appear as input to every gate.
