Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals - VLSI Design and Test - page 319

Table 1. Coefficients of the linear equations with RMSE and correlation coefficient for
different models

Correlation
Coefficient

Model P1 P2 RMSE

1

NMOS 0.1027 -1.032e-09 3.713e-12

PMOS 0.0687 -6.907e-10 1 3.015e-12

Read
column
Model

0.9901

0.03677 2.8e-10 3.258e-10

Write
column
Model

7.963e-12

0.006145 -1.182e-10 0.9998

Stack
Model 1

1

0.002496 -2.394e-11 7.744e-14

Stack
Model 2

1

0.03795 -3.794e-10 1.892e-12

Based on the above pre-characterized models the analytical equations for leakage
current showing width dependency have been obtained. These values have been plotted
to show the comparison of the previous results [1] and the golden results with our work.

Fig. 8. Leakage current of SRAM cell in different phases