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4.3
Read Column Circuit
Read column circuit consists of bit line precharge logic, isolation logic, differential
sense amplifier, and precharge logic for sense bit lines and buffers driving the data
output as shown in figure 4.
In the idle phase, all the signals are deselected and the sense bit lines are at logic
high. Therefore, the leakage current is due to the PMOS of buffers at the output and
sense enable transistor. A model as shown above in fig 5 has been designed to analyze
the leakage current due to sense enable transistor in idle state.
. (21)
During the read phase, the sense enable transistor is on, precharge logic is off and
isolation logic is on for small period of time so that the bit line voltages are sampled
by sense amplifier. Initially, both the bit lines are at high logic and then one
discharges gradually according to the data that has to be read.
. (22)
During write operation, all the signals in read column circuit are deactive. Bitline and
Bitline_bar have complementary values but sense bit lines are at logic '1'.Therefore,
the leakage current is given by:
. (23)
Fig. 5. Model used in read column circuit in
the idle phase
Fig. 4. Schematic of Read Column Circuit.Pch denotes the bit line precharge logic, Iso the
column isolation logic, SensePch the sense amplifier precharge logic, Dsa the Differential sense
amplifier and SenseEn the enable signal. [1]
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