Information Technology Reference
In-Depth Information
For single memory cell,
/
⁄
⁄
⁄
.
(5)
_
.
(forW
N3
=W
N1
)
(6)
For memory core with N
ROWS
and N
COLUMNS,
/
.
(for W
N3
=W
N1
)
(7)
Read Phase.
During Read operation, the bit lines are precharged to V
dd
and the word
line of that particular cell is selected by row decoder. When the word line is enabled,
one of the bit lines connected to a “0” node is discharged through an NMOS transistor.
For single memory cell,
/
⁄
⁄
.
(8)
For memory core with N
ROWS
and N
COLUMNS
(one cell will be in read phase and rest
in idle mode),
.
(9)
Write Phase.
In write phase, the cell selected to write data will have the leakage
current as given by equation (11). The other cells that are unselected will have two
conditions, either bitline ≠ bit or bitline=bit. Therefore, we take 50% probability for
both the cases. Thus, the leakage current is given by,
For single memory cell,
⁄
⁄
.
(WL=1 or WL =0; BIT =BL)
(10)
⁄
⁄
.
(WL=0 or Bit ≠BL) (11)
For memory core with N
ROWS
and N
COLUMNS
(one cell will be in write phase and rest
in idle mode),
.
.
. (12)
4.2
Decoders
For selection of row and column address, row and column decoder have been
designed. The address decoders are controlled by an enable signal. For small single
block memories, single stage row decoder architecture is efficient else multi-stage
architecture is preferable. The above figure shows a 2×4 row decoder. For, higher
order decoder this can be used as a basic block. Similarly, the tree based column
decoders have been designed. The decoders are designed using dynamic circuits.
Dynamic circuits suffer from charge leakage on the dynamic node. If the node is left
floating after being precharged then the node will drift with time. Therefore, we use a
keeper circuit that holds the output at static level.
