Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals - VLSI Design and Test - page 312

Architectural Level Sub-threshold Leakage Power
Estimation of SRAM Arrays with its Peripherals

Nupur Navlakha, Lokesh Garg, Dharmendar Boolchandani, and Vineet Sahula

Malaviya National Institute of Technology,
Department of Electronics and Communication Engineering,Jaipur-302017
{nupurnavlakha,dbool6}@gmail.com,
[e-mail], [e-mail]

Abstract. In this work, an analytical model for estimation of width scalable
architectural level leakage current of the 6T Static Random Access Memory
(SRAM), considering its peripherals is proposed in 45nm technology. Based on
the mode of operation of SRAM (read, write and idle phase), the width
dependent leakage current is estimated at an early stage which reduces design
time and aid to power management. Finally, a SRAM structure (i.e. rows and
columns) dependent model has been evaluated. Referring circuit simulator
(HSPICE) as golden result, the proposed model shows a high accuracy with
error margin less than 5%. The results are 143,127 and 330 times faster than
that achieved by HSPICE simulation in idle, read and write phase respectively.

1 Introduction

A major portion of the processor design includes caches, block memories, predictors,
state tables and other forms of on-chip memory. SRAM applications are wide in
microelectronics, ranging from consumer wireless to high performance server
processors, multimedia and System on Chip (SoC) applications. According to the
International Technology Roadmap for Semiconductors (ITRS), it is projected that the
percentage of embedded SRAM in SoC products will increase further from the
current 84% to as high as 94% by the year 2014.Hence, its increasing demand
requires its analysis at an early stage. Also, this is vital for enhancing various aspects
of chip design and manufacturing.
Earlier, size reduction and better performance were the main concern for the design
of ICs. With the reduction in the transistors size, along with the advances in portable
computing and wireless communication, power dissipation is becoming more
significant. Current trends show that static power dissipation is growing at a faster
rate than dynamic power dissipation. It consumes about 30-50% of the total IC power
consumption.
Leakage power is primarily the result of unwanted sub-threshold current in the
transistor channel in its OFF state. In this paper, we have concentrated on sub-
threshold leakage current.