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Fault Aware Dynamic Adaptive Routing Using LBDR
Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, and Mohit Baskota
Department of Computer Engineering,
Malaviya National Institute of Technology, Jaipur, India
{rimpy,vlaxmi,gaurms,2009ucp853}@mnit.ac.in
Abstract.
Network-on-Chip (NoC) is evolving as an efficient and scalable in-
terconnect architecture for current and future CMP, MPSoC systems. An impor-
tant challenge in NoC design is to choose an appropriate routing algorithm, as it
impacts the NoC performance. As technology scales down to Deep-Submicron
(DSM), on-chip networks are becoming increasingly prone to failures. At higher
level these failures are handled by fault tolerant routing algorithms. Fault toler-
ant routing algorithms avoid faulty regions and route traffic through safe regions.
Currently, routing algorithms are implemented as source or distributed routing.
To handle faults, both source and distributed routing make use of routing ta-
bles. Algorithms implemented with routing tables do not scale well with network
size. Scalable routing implementation, such as Logic Based Distributed Routing
(LBDR) has been proposed for efficient and compact implementation of routing.
LBDR handles faults without using routing table. In this paper we propose a fault
tolerant routing scheme based on LBDR which aims to handle faults while at
the same time addressing network congestion. Proposed method integrates deter-
ministic and adaptive routing schemes to avoid congestion as well as faults that
may be present in the network. Experimental results show the effectiveness of
proposed method in case of single and multiple link failures.
Keywords:
SoC, NoC, LBDR, DyAD, Fault tolerance.
1
Introduction
System on Chip (SoC) packages all complex heterogeneous components of a system
on a single integrated circuit. Due to increasing transistor density, higher operating
frequency driven by increasing computing demand, short time-to-market and reduced
product life cycle have shifted the manufacturers to many-core processors [1]. In many-
core systems large number of cores are assembled together on the same chip forming a
SoC with complex functionality. Major challenge in many-core technology is to provide
high performance while maintaining a low power budget [1].
One important component in these systems is the on-chip interconnect. A novel
packet-switch interconnect, Network on Chip (NoC) [2] has been proposed for SoCs
and chip multi-processors (CMPs) to deal with inefficient traditional interconnects
(higher wire density of fully connected networks and scalability problems of buses)
and to address the high communication demand of future many-core systems. Inspired
from high-performance off-chip interconnects, NoC is a scalable, efficient, flexible and
largely modular approach to interconnect various components [2]. Performance of NoC
