Information Technology Reference
In-Depth Information
Key Observations
1.
The output voltage dips by about 45mV. This is the same dip as seen from
spice-simulation of figure 3. This confirms our earlier assertion that the LDO
is too-slow to react to the initial dip.
2.
It can also be observed that it takes about 1us for the system to get back to
the original voltage. Hence it would not be advisable to start Active mode
operations before 1us, since they typically tend to burn significant power,
and can cause further dip. Thus 1us is the domain-charging latency for this
implementation.
Usage of the Results in the Design
Having done this analysis, the design team will proceed as follows -
1.
The first priority is to guard against functional failure due to voltage dip. If
the voltage for the Already-ON domains (VDDC) dips fatally (below the
min-voltage for which these domains have been designed), then this need to
be fixed first. This will require slowing down the domain-charging, so that
inrush-current is reduced. This can be achieved either by re-sizing the weak
switches to make them still-weaker, or by adding delays between turning-on
successive weak switches. After doing this, the analysis above should be
repeated to confirm that the voltage-dip due to the new inrush current is the
acceptable range. It should be noted though, that slower charging will cost
higher latency.
2.
The second priority is optimize for latency. This can be done only if there is
significant margin on the voltage-dip due to inrush. If such a margin exists,
then the latency can be improved by speeding-up the domain-charging. The
speed-up can be achieved by re-sizing the weak-switches to make them a
little-stronger, or by minimizing the delay (if any) between turning-on
successive weak switches.
7
Conclusions
We have shown a circuit simulation based methodology for early estimation for
inrush current, voltage-drop (induced by the inrush-current), and domain charging
latency. This methodology can be used to select the right tradeoff between the inrush
and the latency. It helps the designers stay in control of the voltage dip at the time of
domain-charging, which could otherwise be fatal for the Already-On and working
domains. At the same time, it allows designers to make their SoC competitive by
designing for the best-possible wakeup latency. The advantages over commercially
available EDA tools are - (1) It does not mandate an “ideal-voltage-source” anywhere
in the circuit, thus making this methodology very suitable for SOCs with on-die
