A Methodology for Early and Accurate Analysis of Inrush and Latency Tradeoffs during Power-Domain Wakeup - VLSI Design and Test - page 300

6 Results

This section shows analysis done on an SoC design. This design has a one power-
domain charging-up, and one Already-ON domain. Also, the Already-ON domain in
this deign happens to be very small compared to the charging-domain (G AO <
0.1*G S ). Multiple instances of a chain of 10-nand gates was used to represent
standard-cell logic in both domains (K=10).

Fig. 7. Voltage waveforms from SPICE simulation of the circuit of Fig. 6

The results of SPICE-simulation are shown in the plots in fig-7. In these plots,
VVDDC and VVDDSW are voltages corresponding to nodes VDDC and VDDSW of
fig. 6. The switch is turned-ON at time t=1us. As the domain charges and VDDSW
rises, the Already-ON domain and the external capacitor provide the charge, and
consequently the voltage on the VDDC dips.
In this case the VDDC drops from 1.2V to about 1.15V which may be acceptable if
the logic in the Already-ON domains has been designed to keep operating at 1.15V
with process-temperature variation. This is an important result because this allows us
to see whether the inrush is serious enough to impact active (already-ON) circuits,
which was one of the stated goals of the exercise.
Another useful output is the waveform for the current through the external
capacitor (Fig 8).
Note that the real instantaneous-values of the current are N PS times the values in
the plot (since our simulation was for a circuit reduced by a factor of N PS .)
The simulation needs to be done at all process-temperature-voltage corners and the
worst-case taken into consideration.