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A Methodology for Early and Accurate Analysis
of Inrush and Latency Tradeoffs
during Power-Domain Wakeup
Vipul Singhal, Ayon Dey, Suresh Mallala, and Somshubhra Paul
Texas Instruments (India), Bangalore, India
{Vipul,a-dey,suresh.mallala,wrik}@ti.com
Abstract.
Power gating is used in almost all Low-power devices to lower
leakage. In this power gating, the three important design parameters are the
domain-wakeup latency (from sleep to active mode transition) time, the inrush-
current when the power switches are turned on, and the voltage dip caused by
the inrush current. Also, the analysis of these parameters has some uniqueness
when there is an on-die power-supply system. In this paper we present a
methodology for analyzing these parameters, followed by a case study
involving analysis of all these parameters using circuit simulation (SPICE) for a
wakeup latency critical low power SoC (System on a Chip).
Keywords:
Power-domain,
Wakeup-latency,
Inrush-current,
Power-
management.
1
Introduction
Power-gating is a common power-saving feature in Low-power SoCs (System on a
Chip). A typical low-power IC has a “Deep-Sleep” mode in which the power-supply
to one or more parts of the design is gated-off by means of switches. Each such
independently controllable part is called a Power-domain. During wake-up from the
deep-sleep mode, the domain has to be charged to full rail-supply through the
switches.
One of the well-known issues associated with un-gating a power-domain is that
initially a large amount of current flows into the domain. This is known as “inrush
current”. As a result of the inrush current, the power-supply rail may see a sharp
transient-drop in voltage. Since the power-rail is shared with other power-domains
(which may be up and running), this drop can be fatal for their functionality. The usual
solution is to slow-down the charging. This is achieved by using a switch-cell that
consists of a strong-switch and a weak-switch (Fig 1.). The strong switches are used
for operation in active mode, while weak switches are used to slowly charge-up the
power domain, so that the inrush current is minimized. This concept is common in
power-management-related literature [1].
Often, such Low-power SoCs are used in real-time system-control applications.
Although the SoC may remain in standby mode or ”deep-sleep” mode for a long time
