Information Technology Reference
In-Depth Information
6
Results
The proposed methodology was used to build and integrate IP level verification
testbench around SCI [serial communication interface] which had 4 interfaces (as
described above). The generated testbench was verified with Cadence IUS and
Synopsys VCS simulators. As an initial step the integration time was reduced from
around 2 days to half hour with case1 and case2 being true.
Case1: The integration related data was available for the tool to run.
Case2: The engineer has good knowledge of verification language.
Case3: The engineer has directory structure, Company's internal methodology
knowledge to write interconnection and more important the minor details of the
protocol. With case 2 and 3 the integration time without tool was around 1 day. So
based on these results with all cases 1, 2 and 3 being true, the approximate connection
time per interface is around 1.5 man hour without automation. Extrapolating this
statistics for a medium sized SoC having around 65 interfaces , the testbench integration
job would take approximately 3 Man weeks and with automation it can be cut down to
few days, including the time needed for creating top level tabular data base.
7
Conclusion
The proposed work introduced a novel flow and methodology for testbench
automation. The tool supporting methodology was also developed. The main aim of
the idea was to reduce testbench creation time both at IP and SoC level. Initially some
of the information obtained from user in tabular format for a specific protocol. The
same information can be reused at SoC level by doing some minimal changes. The
scope of manual error in making VIP instance connections to DUT is greatly reduced
as this task is automated. The tool also develops VIP in case if it non-existing. Finally
a fully functional UVM testbench is delivered. Application results have shown
considerable amount of time saving in complete process of verification.
References
[1]
UVM,
https://verificationacademy.com/topics/
verification-methodology
[2]
OVM,
https://verificationacademy.com/topics/
verification-methodology
[3]
VMM,
http://www.synopsys.com/community/interoperability/
pages/vmm.aspx
[4]
Agile Soc,
http://www.agilesoc.com/2012/05/07/
wasted-effort-spent-in-verification/
[5]
Da Silva, K.R.G., Melcher, E.U.K., Araujo, G., Pimenta, V.A.: An automatic testbench
generation tool for a System C functional verification methodology. In: SBCCI 2004:
Proceedings of the 17th Symposium on Integrated Circuits and System Design (2004)
[6]
Cho, K., Kim, J., Jung, E., Kim, S., Li, Z., Cho, Y.-R., Min*, B., Choi, K.-M.: Reusable
Platform Design Methodology for SoC Integration and Verification. In: International SoC
Design Conference (2008)
[7]
Synopsys uvmgen User Guide
