Information Technology Reference
In-Depth Information
To maintain stringent standards in terms of coding practices and guidelines the VIP
has to undergo different checks to ensure quality. These checks can be of different
categories like naming conventions, coding styles, file formats etc. This is done to
make sure that the verification components used, also facilitate reuse and reduce the
number of iterations during the verification cycle.
3.2
Importance of Directory Structure and Integration Tool
For large designs and equally large and complex testbenches, automation is needed at
all levels of design and verification process. The automation proposed for integration
is easy to implement only when there is standardization in SOC and IP data
management. The process of design and testbench integration expects a complex and
conditional file collection for large number of IPs and VIP data. This is facilitated by
following a standard directory structure and disciplined naming conventions for all
design and verification collaterals. The standard directory structure enables the reuse
of standard IP blocks and portability of SOC data. Now after having all the VIPs in
place the details given by the user are used to connect the VIPs and configure them.
Sample test cases [5, 6] which use the VIPs to communicate with the design under
test are also produced.
The next step is to integrate the VIPs with the DUT which is again done with the
help of user given tabular inputs. But the aim is to get it correct by construction
methodology. The connections are made based on manual inputs, thus can be error
prone. So as to maintain quality and to ensure thoroughness, formal tools are used to
verify connections.
3.3
Use of Formal Engine to Verify the Connection and Interface Coverage
The usage of formal methods to ensure quality and correctness of the connections has
been proposed here. The source of error in connection information is either manual
entry of the connection database or because of signal and port width mismatches.
There could also be instances where port names or signal names are missing .All these
discrepancies will be rectified here by running connectivity verification checks by
using formal tools, thus ensuring completeness. For checking the missing port lists,
options from the formal tool have been incorporated to show uncovered ports. As an
input to the formal tool a dummy module is created with the port list comprising of
the signals listed in the input CSV file. Connectivity assertions between
corresponding pair of signals in the DUT top module and the dummy module created
previously are generated. By following this, any error in the specification of the
signals will be caught. This coverage driven connectivity checking provides strong
basis at IP level leading to golden database creation.
So far IP level testbench creation has been discussed, SOC level poses different
challenges; for example at SOC level although the need for writing of new VIPs is
minimal as VIPs used at IP level already exist but the number of such VIPs to be
connected is very large . A new methodology has been introduced to reuse the
connectivity information of IP level at SoC level which simplifies the task of creating
the testbench.
