Automatic Test Bench Generation and Connection in Modern Verification Environments: Methodology and Tool - VLSI Design and Test - page 284

Automatic Test Bench Generation and Connection
in Modern Verification Environments:
Methodology and Tool

Rohit Srivastava, Gaurav Gupta, Sarvesh Patankar, and Nandini Mudgil

Freescale Semiconductor Pvt Ltd.
[e-mail]

Abstract. Due to complex designs and time to market pressure verification
closure is the bottleneck in ASIC/SoC design. Hence setting up a constrained
random testbench environment seems to be a difficult task, especially when we
consider that environments need to be flexible, scalable, and reusable. Although
standard verification methodologies such as UVM [1], OVM [2] or VMM [3]
help to an extent, but then creating testbench environment still consumes a lot
of time. This calls for the need of testbench automation. There has been a lot of
development in testbench automation techniques but still the problem of
connectivity between the VIP interface and DUT remains unsolved which
consumes considerable amount of time at SoC level. To solve this problem a
novel technique has been proposed. The aim is to achieve a correct by
construction technique to get the various existing components from IP level and
make the automatic connection of the verification component with the design
under test.

Keywords: SoC, Functional Verification, Testbench Automation, Verification
Methodology, UVM, OVM, VMM.

1 Introduction

This paper presents a method to reduce time in testbench creation and setup of
verification environment. Writing a new environment from scratch requires
experience about the methodology and testbench environment, it may take anything
from days to weeks depending upon the experience of the engineer. Nowadays SoCs
are quite complex, typically they have multiple cores with hundreds of peripheral IPs
and the interconnecting logic itself has very large number of interfaces. So, testbench
bring up takes around 2-3 weeks for these SoC's. Apart from that, manual mistakes in
the component connections at the later stage take many weeks to debug and fix.
According to an industrial survey [4] 32% time is consumed in debugging. Writing
and Running test cases takes around 27% while around 28% of time is consumed in
testbench development itself. If the time required for testbench development is
reduced, then certainly the time to market for the product under development can be