Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-k Spacers - VLSI Design and Test - page 271

time is the time period from 50% point of WL transition until 50-100mV voltage
difference develops between the bitlines. To achieve a reduced read access time is
another metric in read mode and depends on the maximum current flowing through
the access and the pull-down transistors. In write operation, values “0” and “1” are
applied to BL and BLB respectively with the access transistors turned on to flip the Q
from “1” to “0”. Similarly, write-margin and write access time are calculated for write
operation. The write access time is measured between the time when WL reaches to
50% of V DD and the time when a node QB reaches to switching threshold voltage of
another inverter. To find SNM; the conventional method is used [10].
Fig. 5. (a) Conventional tied-gate 6T-SRAM cell configuration, (b) Percentage change in hold-
SNM, (c) read-SNM as function of spacer material with varying underlap length ( L un )
Fig. 6. Change in (a) write-margin, (b) read-access time, and (c) write-access time as function
of spacer material with varying underlap length ( L un )
Fig. 5(b), 5(c) and 6(a) shows the percentage change in hold, read and write noise-
margins respectively, with respect to reference device as function underlap length and
spacer materials. For low- k spacer material, a marginal change in hold and read SNMs
are observed as an increase in underlap length. Incorporation of the high- k spacer
material will enhance the SNMs up to 10-12% due to increased electrostatic integrity.
The read and write access time variations are shown in Figs 6(b) and (c), respectively.
It is observed that both read and write access time degrades because of reduction in
the drive current with increasing underlap. The read access time degrades more rapid-
ly with low spacer k value. However, write access time worsens more with high- k
spacers due to increased gate-capacitance that enhance word-line capacitance. For
SRAM applications, it is observed that for L un near about 4nm provides superior per-
formance improvements and thereafter, the cell designs metric degrades.