Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-k Spacers - VLSI Design and Test - page 267

Optimization of Underlap FinFETs and Its SRAM
Performance Projections Using High- k Spacers
Pankaj Kr. Pal, Brajesh Kumar Kaushik, and Sudeb Dasgupta
Microelectronics & VLSI Group, Department of Electronics & Communication Engineering
Indian Institute of Technology-Roorkee,
Roorkee, Uttarakhand, India
[e-mail], {bkk23fec,sudebfec}@iitr.ernet.in
Abstract. The undoped underlap region is unavoidable in devices with gate length
16nm or less to reduce SCEs. For the first time, this research paper addresses the
complete underlap optimization analysis along with the spacer engineering from
the device to circuit perspective. We elaborate the impact of underlap on drive cur-
rent, leakage current and their ratio. The fringe capacitance component (included in
total-gate capacitance) and the relative change in a drive current-to-capacitance is
also investigated that helps to optimize circuit delay. Furthermore, the impact of
underlap and spacer dielectric on various SRAM designs metric is investigated that
mitigate read/write conflict. It has been observed that optimal underlap improves
the SRAM stability and access times. For SRAM applications, underlap length
near about 4nm provides superior performance improvements and thereafter, the
cell designs metric degrades.
Keywords: Underlap FinFET, short channel effect (SCE), SRAMs, static noise
margin (SNM), access-time, high- k spacers.
1 Introduction
As Intel progresses to use the 3D tri-gate transistors commercially in the 22nm tech-
nology node, a strong interest has emerged among semiconductor industries in form-
ing 14nm and 10nm bulk FinFET. However, there are several challenges that need to
be addressed. The undoped underlap region emerges as an attractive option to reduce
leakage current and SCEs such as DIBL, GIDL, and subthreshold slope but at the
expense of increased source/drain series resistance. Furthermore, increased
source/drain (S/D) series resistance ( R S/D ) degrades to drive current ( I on ). For G-S/D
underlap FinFET device; spacer engineering plays an important role. When the over-
lap is removed, the fringe field contribution modulates the source-drain channel con-
ductivity. Along with the SCE- R S/D trade-offs, another trade-off found is in between
R S/D and fringe capacitance C fr , due to inner and outer fringe field lines. As the fringe
capacitance increases, it accumulates more inversion charges in the undoped underlap
region that reduces series resistance with improved SCEs. Therefore, the spacer ma-
terial and the underlap length need to be carefully optimized [1].
From the circuit perspective, high- k spacers increase the fringe capacitance ( C fr )
component of the total gate capacitance ( C GG ) that worsens the circuit in terms of