CPK Based IO AC Timing Closure to Reduce Yield Loss and Test Time - VLSI Design and Test - page 266

long as process doesn't shift, thus removing test pattern from production list. Hence,
ATE test time is reduced. As chances of AC specification failure are comparatively
less, so, there is an increase in yield of SoC. All these contribute to the increase of
gross margin of SoC. As per our knowledge, this is the first proposal regarding CPK
based I/O timing closure in STA for yield improvement and reduction of test time.
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