Information Technology Reference
In-Depth Information
Table 4.
(
Continued
)
1.330
1.551
1.770
>=2
t
UEIVKH
i/p setup
4
min
0.378
0.474
0.560
>=2
t
UEIXKH
i/p hold
1
min
4.204
4.678
5.242
>=2
t
UEKHOV
o/p valid
1
min
QE
UTOPIA
4.204
4.678
5.242
>=2
t
UEKHOV
o/p valid
10
max
3.214
3.646
4.028
t
UEKHOX
o/p valid
1
min
<2
3.214
3.646
4.028
t
UEKHOX
o/p valid
10
max
<2
>=2
t
UIIVKH
i/p setup
6
min
3.660
4.181
4.860
QE
UTOPIA
t
UIIXKH
i/p hold
0
min
-0.740
-0.530
-0.400
>=2
1.280
1.546
1.820
>=2
t
TUIKHOV
o/p hold
0
min
1.280
1.546
1.820
>=2
t
TUIKHOV
o/p hold
8
max
>=2
t
UIKHOX
o/p hold
0
min
0.440
0.873
1.100
0.440
0.873
1.100
>=2
t
UIKHOX
o/p hold
8
max
6
Implementation Challenges
There are various challenges that need attention for implementation of this approach-
A.
Standard deviation data from previous Si
Getting correct data from a previous Si of same technology node could be a chal-
lenge. There could be non-technical issues for getting this data from product engineer-
ing team, as it requires extra effort for churning huge data correctly.
B.
Extra effort in I/O timing closure in STA
As design is more constrained due to this parallel hardware specification, extra ef-
fort is required to close I/O AC timing wrt traditional approach.
C.
Changes in design for I/O AC timing closure
As a consequence of new hardware specification, it might happen that the logic
which is responsible for meeting the I/O AC timing is not adequate with proposed
approach to meet required CPK. Hence, we may have to change certain portion of
logic to meet this requirement.
7
Conclusion
In this paper, we have proposed a CPK based approach to meet required I/O AC tim-
ing for different peripheral interface, taking standard deviation from previous Si of
same technology node. This method has been applied to various SoC [1][2][3][4][5]
and it has yield good result. As margin on this I/O specification is adequate, therefore,
test engineer can confidently guarantee that this specification will never fail on Si as
