Information Technology Reference
In-Depth Information
Standard Deviation (
) = 0.19 (for e.g.)
CPK = (USL-
)/3*
= 4.86 ns
Therefore, targeted design specification for maximum output delay to meet CPK of
2 should be taken as 4.86ns.
5
Case Study
This approach has been followed for SoC [1][2][3][4][5].
5.1
Parallel HW Specification for Different Peripherals
Table 3.
: Parallel Hardware Specification of different interfaces for CPK of 2, 1.67, 1.33 & 1
t
NIKHOX
o/p delay
0.5
Min
1.25
1.00
0.83
0.71
1.35
2.00
t
NIKHOV
o/p delay
4
Max
2.46
2.63
2.83
3.05
2.20
2.00
eSPI
t
NIIVKH
i/p setup
5
Min
2.91
3.12
3.38
3.68
3.20
1.33
t
NIIXKH
i/p hold
-1
Min
-1.96
-1.69
-1.48
-1.32
-2.40
2.00
t
USIVKH
i/p setup
4
Min
2.72
2.87
3.05
3.31
1.80
2.00
t
USIXKH
i/p hold
1
Min
0.55
0.59
0.65
0.71
0.54
2.00
USB
t
USKHOV
o/p delay
7
Max
5.38
5.60
5.84
6.09
5.00
2.00
t
USKHOX
o/p delay
2
Min
2.86
2.67
2.50
2.35
3.80
2.00
t
LBIVKH
i/p setup
6
Min
4.38
4.58
4.81
5.06
4.20
2.00
t
LBIXKH
i/p hold
1
Min
0.71
0.75
0.79
0.83
-2.50
2.00
t
LBIVKL
i/p setup
6
Min
4.62
4.80
5.00
5.22
4.32
2.00
eLBC
t
LBIXKL
i/p hold
1
Min
0.77
0.80
0.83
0.87
-2.70
2.00
t
LBKLOV
o/p delay
1.5
Max
0.78
0.84
0.93
1.02
0.60
2.00
t
LBKLOX
o/p delay
-3.5
Min
-2.52
-2.65
-2.78
-2.93
-1.10
2.00
t
SHSKHOX
o/p delay
3
Max
1.10
1.23
1.40
1.61
0.80
2.00
t
DMIVKH
i/p setup
3
min
1.88
2.00
2.14
2.31
1.00
2.00
t
DMRDIXKH
i/p hold
3.5
min
2.19
2.33
2.50
2.69
1.60
2.00
TDM
t
DMFSIXKH
i/p hold
2
min
1.25
1.33
1.43
1.54
0.75
2.00
t
DMTKHOV
o/p delay
14
max
8.75
9.33
10.01
10.77
6.25
2.00
TDM
t
DMTKHOX
o/p delay
2
min
5.00
4.01
3.33
2.86
5.00
2.00
t
DMFSKHOV
o/p delay
13.5
max
8.44
8.99
9.65
10.38
7.50
2.00
t
DMFSKHOX
o/p delay
2.5
min
6.25
5.01
4.16
3.57
6.25
2.00
