Information Technology Reference
In-Depth Information
approaches [7-12] to reduce the ATE test time. The approach proposed in this paper is
another effort in this direction. It may also happen that, marginally passing AC I/O
specification start to fail at some PVT condition on production during product life
cycle resulting yield loss. Therefore, it is obvious that one should build sufficient
margin on I/O AC timing in design phase of Si, so that it never fail on Si when tested
on ATE. But, quantification of “how much margin” needs to be built is a difficult
question to answer. In this paper, an attempt has been made to quantify the extra mar-
gin to be built on I/O AC timing closure based on required CPK on Si. CPK measures
how close you are to your target and how consistent you are around your target. For
example, a person may be performing with minimum variation, but he can be away
from his target towards one of the specification limit, which indicates lower CPK. On
the other hand, a person may be exactly at the target on an average, but the variation
in performance is high. In such cases, CPK will be lower. CPK will be higher when
you are meeting the target consistently with minimum variation. For any SoC quali-
fication, every I/O AC specification needs to meet a particular CPK number. Here, a
parallel hardware specification is created for different I/O interfaces with CPK value
of 2, 1.67, 1.33 and 1. SoC designers are asked to meet I/O AC timing in STA for
CPK=2 first. If I/O AC specification is more stringent at CPK=2 and unable to meet
then, option for CPK=1.67 is considered. Similarly, if 1.67 is difficult to meet then
1.33, if not then option for CPK=1 is considered. In this way, a well defined directed
approach has been followed to meet the I/O AC timing with required margin to be
built on production.
The contents of the paper are organized as follows: Section 2 depicts a typical net-
working SoC architecture with different peripherals. In Section 3, basic of CPK is
described to aid the understanding of this method. Section 4 focuses on how parallel
hardware specification is made based on required CPK. Section 5 provides result of
this approach on real Si. Section 6 lists the various challenges for implementing this
method. Finally, section 7 concludes the paper.
2
Architecture of Networking SoC P1020
Fig.1 shows the architecture of P1020 SoC with different peripherals like dual data
rate (DDR), enhanced local bus controller (eLBC), time division multiple access
(TDM), serial peripheral interface (SPI), universal serial bus 2.0 (USB), etc. These
digital peripheral interfaces communicate with the external world using their respec-
tive input/output (I/O) signal. Traditionally, SoC designer will meet the AC I/O tim-
ing for all these peripherals as per their hardware specification as depicted in Table 1
and Fig.2
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters
of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters
of functional block)(reference)(state)(signal)(state) for outputs. For e.g. tNIKHOV
Search WWH ::




Custom Search