CPK Based IO AC Timing Closure to Reduce Yield Loss and Test Time - VLSI Design and Test - page 257

CPK Based IO AC Timing Closure
to Reduce Yield Loss and Test Time

Sandip Ghosh and Rohit Srivastava

Freescale Semiconductor India Pvt. Ltd
Plot-18, Sector-16A, Flim City, Noida-201301, India
{sandip.ghosh,rohit.srivastava}@freescale.com

Abstract. With growing complexities of SoC, number of on-chip peripheral is
also increasing and it is mandatory for SoC engineer to meet the I/O AC timing
in Static Timing Analysis (STA). But, at times, it is found that I/O timing are
failing or passing marginally, when Si is tested on Automated Testing Equip-
ment (ATE). Failing of I/O AC specifications leads to extensive debugging of
Si on ATE, resulting test time increase, yield loss & further revision of Si. This
paper proposes a method whereby extra margin has been built on I/O AC timing
closure of all peripherals in the design phase itself, keeping targeted Coefficient
of Process Capability (CPK) in mind. It has been shown that using this ap-
proach, most of the peripherals meet ~ CPK of 2 when tested on different SoC.
Consequently, ATE test time and yield loss is reduced.

Keywords: Co-efficient of process Capability, Static Timing Closure, Automated
Testing Equipment, I/O AC Timing.

1 Introduction

Problem of I/O AC timing failure or having a less margin of different peripheral inter-
faces is inherent in many SoC. It is mandatory to close I/O AC timing in BCS and
WCS for design sign-off. In BCS scenario, process is faster/less delay, voltage is kept
high and temperature is low. Whereas in WCS, Si process is slower/lager delay, vol-
tage is low and temperature is high. But, we tend to get failure or a less margin when
Si is tested on ATE across process-voltage-temperature (PVT) condition. This could
be due to various reasons, for example, I/O library characterization not accurately
matching with Si behaviour, measurement uncertainty on ATE, interference or any
parasitic effect, etc. Whatever may be the reason, the penalty is heavy in terms of time
consumed on ATE to nail down the I/O AC timing failure and subsequent Si revision.
Also, it leads to increase in ATE test time incurred due to running pattern on produc-
tion which could have been removed if we had sufficient margin of I/O AC timing.
There is huge push in semiconductor industry to reduce ATE test time as it has direct
impact on product viability and gross margin. International Technology Roadmap for
Semiconductor (ITRS) [6] has also given effort in this direction. There are various