Information Technology Reference
In-Depth Information
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Read wordline (RWL) is separate from write wordline (WWL).This means that
for read access the new cell only asserts RWL to enable the left switch pass
transistor and the right pass transistor is kept off. This is opposite to conventional
6T/ST cell which uses both pass transistors by asserting common WL for read or
write operation. Hence, the read access is performed only through the left side of
the cell using RBL precharged high and then asserting the RWL. On the other
hand, the write operation is accomplished only through the right side of the cell
by enforcing the WBL to the desired value and then asserting the WWL,
independent of the left side. With this structure the symmetric topology is no
longer satisfied.
Fig. 2.
Asymmetrical Schmitt Trigger Bitcell
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Simulation Results
HSPICE simulations were performed using 45nm predictive technology model for
MOS. Typical NMOS (PMOS) threshold voltage is 466mV (412mv).The
conventional 6T bitcell and proposed AST bitcell are compared for various SRAM
metrics. For 6T cell, transistor widths WPU/WAX/WPD are 80nm/160nm/240nm,
respectively. For AST bitcell, extra transistors NFL/NL2 are of minimum width
(80nm) while other transistors have the same dimensions as those of 6T cell.
The ST bitcells consumes approximately 2X area compared with the 6T cell.
Hence, in order to estimate the operating conditions, it is only fair to compare the
bitcells under Iso-area condition [7][10].
Fig. 3 compares the leakage current of AST with conventional 6T bitcell and ST.
The results clearly demonstrate that, under Iso-area conditions, the leakage current of
proposed cell is less compared to that of 6T cell and ST cell in subthreshold
operation. Fig. 4 plots Iso- area power consumption vs. supply voltage (mV) of 6T,
ST cell and proposed bitcell and it can be seen that the proposed AST consumes very
less power compared to other in subthreshold operation making it a good choice in
low power applications.
