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allowing the contents of the cell to be read out to the bit line say BL (and its inverse)
to the not bit (BR) line. To write the cell, we again set the word line high, but this
time we set the bit line (and its inverse) to the value we wish to store, forcing the cell
into the appropriate state.
2.1
Conflicting Read vs. Write Design Requirement in 6T bitcell
For reliable read operation, the design requirement is such that the data should not be
flipped. However during the write operation, the design requirement is such that the
data should be flipped as easily as possible. This is the fundamental conflicting design
requirement in the conventional 6T bitcell. This is because; the same pair of access
transistors is used to initiate read/write operation in a 6T cell. Traditionally device
sizing has been adopted to balance the read versus write design requirements. With
increased process variations, satisfying the conflicting requirements during read-write
operation is becoming very challenging [8]. This degrades the scalability of the
SRAM cell as well. Moreover, device sizing is not effective for improving the cell
stability at very low supply voltage [9]. Hence there arises a need for a novel design
approach for successful low voltage operation of SRAM bitcells in nano-scaled
technologies.
In order to resolve the read versus write conundrum in the 6T cell, Schmitt trigger
principle for the cross coupled inverter pair had been proposed [10]. A Schmitt trigger
is used to modulate the switching threshold of an inverter depending on the direction
of the input transition.
3
Proposed Asymmetric SRAM Bitcell
Fig. 2 shows the schematics of proposed asymmetrical Schmitt trigger based bitcell.
For maintaining the clarity of discussion, the bitcell configuration in [10] is termed as
ST bitcell while the bitcell we proposed is termed as AST bitcell hereafter in this
paper. The AST bitcell have 10 transistors, 2 wordlines (WLL /WLR) and 2 bit-lines
(BL/BR). Transistors PL-NL1-NL2-NFL form ST- I inverter while PR-NR1-NR2-
NFR form ST- II inverter. Feedback transistors NFL/NFR raise the switching
threshold of the inverter during the 0→1 input transition giving the Schmitt trigger
action.
Asymmetric cell (AST) differs from usual 6T and Schmitt trigger based SRAM cell in
following manner.
Read bitline (RBL) is separate from write bitline (WBL). This means that the
read operation is performed independent of the right side bitline, unlike the
traditional 6T/ ST cell which uses both bitlines simultaneously for read access
and write operation.
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