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to Noise and Distortion Ratio (SNDR) along with the resolution of the ADC
employing FDSM architecture will be limited by the VCO non-linearity [5][6][7].
Thus, a linear frequency-voltage (f-V) tuning characteristics and wide tuning range of
the VCO are essential for high performance PLL and FDSM based ADCs.
A VCO can be implemented using LC oscillator, ring oscillator and relaxation
oscillator. However, ring oscillator has been a popular choice for VCO as it occupies
less area, has wide-tuning range and can be easily integrated on-chip as compared to
other oscillator architectures. In literature [8][9][10], design methodology of ring
VCO has been addressed considering center frequency, power dissipation, jitter,
tuning range as the specification parameters. The optimization is done for area and
center frequency resulting in optimal transistor sizes. Tuning linearity in VCOs has
been addressed using techniques such as an on chip servo loop [11], post-correction
techniques [12], source degeneration [13], and a Frequency Locked Loop (FLL) as
VCO [14]. This paper proposes a design methodology for a CMOS current starved
ring voltage controlled oscillator considering tuning bandwidth and linearity as the
design parameters without additional circuitry and thus reducing the power
consumption. The proposed designed methodology enhances tuning linearity and
consequently tuning range for the current starved ring VCO. The design has been
implemented in UMC 0.18 µ m CMOS technology at 1.8 V supply voltage. The
overall circuit consumes 260 µW at 404.5 MHz, has a wide tuning range of 66 MHz
to 875 MHz having 94.5% tuning linearity. However, supply rejection and noise are
the major issues of ring VCO and research has been done to mitigate this problem
[15], [16]. The present work assumes a constant supply voltage from a stable supply
regulator. In the next section, the analysis and design of the current-starved VCO
design is discussed along with the comparison of conventional [13] and proposed
design procedure. In section 3, the outline of the proposed design procedure is
presented. Section 4 presents the simulation results and finally conclusion is given in
section 5.
2
Current-Starved VCO Design
A Current Starved Voltage Controlled Oscillator (CSVCO) as shown in Fig. 1
consists of a ring oscillator formed by an odd chain of inverters (M p , M n ) biased by
current source and sink (M ps , M ns ). The transistors (M pb , M nb ) act as the bias stage and
bias current (I bias ) is mirrored from bias stage to each stage of the ring oscillator.
The time taken by each inverter stage of the ring VCO to charge/discharge the total
capacitance (C tot ) from 0 to V SP with I bias when CSTs are in saturation region is given
by
V SP
I 1
t C
The total capacitance is the sum of the input and output capacitances at each output of
the inverter stage and is given by
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