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extending battery life of portable electronic devices like smart phones, digital
cameras, biomedical chips etc.
Different power reduction techniques like voltage scaling, pipelining, device &
interconnect sizing and switching activity reduction have been implemented at
device/circuit/architectural level. Among these, supply voltage scaling has remained
one of the first choice of designers. The dynamic power can be reduced quadratically
and leakage power linearly to first order by reducing supply voltage [2].
In a given process technology, the process constraints such as gate oxide limits the
maximum supply voltage (V max ) for transistor operation and for a given performance
requirement, the minimum supply voltage (V min ) is limited by increased process
variation and sensitivity. With technology scaling, the V max increases while the V min
increases. Therefore for low power operation, the V min has to be lowered further to
increase the SRAM bitcell operation range.
1.1
Process Variation
The major roadblock that designers face is process variation, as high performance
processors move to sub 45nm technologies. The process parameter variation results in
variation in maximum operating frequency and power consumption in fabricated dies
[3]. Process variation can be due to variation in parameter, voltage and temperature.
Inability to precisely control the fabrication process at nanometre technologies, results
into parameter variation. Parameter variations can be mainly classified in to two
categories- (i) Die to Die (D2D) variations, which affects all the transistors in a lot or
wafer equally and (ii) With-in die (WID) variations, consisting of systematic and
random components, causes electrical characteristics to vary across a die [4]. For a
given design, both, power supply and temperature vary from chip to chip and within
chip. Voltage variation can be caused by IR drops in the supply networks or by L d I/ d t
noise under changing load. Spatially and temporally varying factor causes
temperature variations. All these variations cannot be tolerated as technology scales to
smaller feature sizes.
In ultra low power designs, the sensitivity of circuit parameters increases with
reduction in supply voltage. Memory cells are most sensitive to device variations
causing device mismatch for several reasons. Therefore the process variation limit the
circuit operation in sub threshold region, particularly in SRAM cells where minimum
sized transistors are used. For several reasons memory cells are most sensitive to
device variation which results in device mismatch. Usually the devices used in
smallest memory cell for a given process, is smaller than the devices allowed
elsewhere in the design [5].
1.2
Earlier Work on Process Variation Tolerant SRAM Bitcell
The 6 transistor (6T) cell which uses a cross-coupled inverter is the basic memory
bitcell used in SRAM designs. Several SRAM bitcells have been proposed to meet
different design goals such bitcell area, low voltage/ low power operation, timing
specifications, bit density and reliability. To improve process variation tolerance,
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