Variation Robust Subthreshold SRAM Design with Ultra Low Power Consumption - VLSI Design and Test - page 242

Variation Robust Subthreshold SRAM Design
with Ultra Low Power Consumption

Saima Cherukat and Vineet Sahula

Department of Electronics & Communication Engineering,
National Institute of Technology, Jaipur, India
[e-mail], [e-mail]

Abstract. Continued scaling of CMOS technologies has resulted in process
variations emerging as a critical design concern. The power consumption
requirement in portable devices is even more strictly constrained for extending
the battery operating lifetime. In this work, we propose an asymmetrical
Schmitt trigger based SRAM cell, suitable for ultra low power applications. It
addresses the fundamental conflicting design requirement of read versus write
operation of conventional 6T cell. A built-in feedback mechanism proposed for
the cell, makes it more robust against process variations. Usually, a Schmitt
trigger cell configuration has been used in literature for improving stability of
inverter-pair. We propose asymmetrical cell-configuration as modification over
this usual Schmitt-trigger based configuration so that the design becomes more
tolerant of mismatch in neighboring transistors. Simulation results show that
proposed bitcell operates on a very low leakage current and with much less
power dissipation compared to 6T cell.

Keywords: Low voltage/Subthreshold SRAM Design, Low power SRAM,
Process variation, Schmitt trigger.

1 Introduction

It is expected that more than 90% of the die area in future systems-on-chip (SoCs)
will be occupied by SRAM and the requirements of higher density and low power
SRAMs are increasing exponentially. The main sources of power consumption in
digital Complementary Metal Oxide Semiconductors (CMOS) circuits are logic
transitions, short circuit currents that flow directly from supply to ground when both n
and p sub network conducts simultaneously and leakage current that accounts for
static power dissipation. The active power dissipation in the switching parts of the
circuit increases with improved performance and increased density with each
technology generation. Leakage mainly consists of gate leakage and subthreshold
leakage. The magnitude of leakage current is no longer negligible and it plays a
significant role in total power consumption at lower technology nodes. For portable
devices developed for 65nm technology node, it is estimated that subthreshold
leakage power will account for about 50 percent of the total power consumption [1].
Ultra low power design is always on demand as it can meet the requirement of