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A Novel Design Methodology for High Tuning Linearity
and Wide Tuning Range Ring Voltage Controlled
Oscillator
Gudlavalleti Rajahari 1,2 , Yashu Anand Varshney 1,2 , and Subash Chandra Bose 1,2
1 CSIR-Central Electronics Engineering Research Institute (CSIR-CEERI),
Pilani, Rajasthan, India
{rajahari,subash}@ceeri.ernet.in
2 Academy of Scientific and Innovative Research
yvarshney@gmail.com
Abstract. This paper presents a novel design methodology of a CMOS current
starved ring Voltage Controlled Oscillator (VCO) for wide tuning range and
high linearity. The f-V tuning characteristic of the ring VCO depends on the
current-voltage (I bias -V control ) characteristic of the replica bias and region of
operation of current sources/sinks transistors (CSTs). The proposed design
methodology linearizes the I bias -V control characteristic and ensures the CSTs to
operate in saturation region during switching and consequently enhances the
tuning range without additional circuitry. The design is implemented in UMC
0.18 µm CMOS technology at 1.8 V supply voltage. The overall circuit
consumes 260 µW power at 404.5 MHz, has a wide tuning range of 66 MHz to
875 MHz having 94.5% tuning linearity.
Keywords: Ring VCO, Wide Tuning Range, Tuning Linearity, Current
Starved, Design Methodology.
1 Introduction
Phase-Locked Loop (PLL) is one of the important analog/mixed signal circuits for
clock generation, frequency synthesis etc ., in a System-on-Chip. VCO is the critical
building block that affects the tuning range, jitter, power and area of the overall PLL.
A linear and wide tuning range of the VCO is an important performance parameter in
various applications [1][2]. A linear frequency-voltage (f-V) tuning characteristic of
the VCO leads to a constant loop gain K VCO (Hz/Volt) providing the widest possible
tuning range to the PLL. A nonlinear and high K VCO can result in increasing noise and
spurious power of the PLL owing to frequency modulation of the control voltage
noise [3]. Such non-linearity also degrades the closed loop performance parameters
such as loop bandwidth and settling behavior of PLLs [4]. In Frequency based Delta
Sigma Modulator (FDSM) where VCO acts as an alternative to op-amp based
integrator has performance degradation due to VCO non-linearity. If the VCO is
nonlinear, it will introduce a harmonic distortion to the output signal. Also, the Signal
 
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