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CMOS ASIC Design of a High Performance Digital
Fuzzy Processor That Can Compute on Arbitrary
Membership Functions
Anirban Guha and Shubhajit Roy Chowdhury
Center for VLSI and Embedded Systems Technology
International Institute of Information Technology, Hyderabad - 500032, India
anirban.guhaug08@students.iiit.ac.in, src.vlsi@iiit.ac.in
Abstract.
The paper presents the CMOS ASIC design of a digital fuzzy proces-
sor, that can compute on arbitrary membership functions. The architecture ex-
ploits pipelining and parallelism to reduce the inferencing delay. The processor
has been designed to operate at a frequency of 2 GHz using a power supply of
1 V. For a system with 256 active rules, the circuit has delay of 1285 ns and
power dissipation of 70.5 mW. The set of common antecedents for a group of
rules are stored separately, leading to reduction in delay and power dissipation.
The performance of the proposed circuit has been compared with state of the art
RISC and CISC processor architectures, and found to dissipate much less power
and has much less delay.
Keywords:
Fuzzy processor, Membership function, Antecedents, Rules.
1
Introduction
Fuzzy processors are commonly used in different control systems such as heating and
air conditioning systems, automobile braking, washing machines, industrial automa-
tion etc. Fuzzy systems take the uncertainties in data into considerations while making
decisions. The hardware implementation of fuzzy logic has been investigated in sev-
eral works, with the first proposal coming from Togai and Watanabe [1]. The usage of
general purpose processors in fuzzy logic computations has been mentioned in [2-5].
However, these are not suitable for real time applications where high speed infencing
is needed, within hard real time deadline. Hardware dedicated for fuzzy computations
has been developed for high speed applications [6-13]. However the use of FPGA
based architectures adds flexibility in implementing the fuzzy system on chip [14].
Roy Chowdhury and Saha have proposed a high performance FPGA based fuzzy
processor based on parallel-pipelined architecture in [15].
The current research is aimed at the ASIC design of a digital fuzzy processor. The
processor has been designed to compute on arbitrary membership functions. This
leads to better accuracy in results. The set of common antecedents for a group of
fuzzy rules are stored separately in memory. This leads to reduction in memory space,
delay and power dissipation.
