Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM - VLSI Design and Test - page 9

[6] Wicht, B.: Current Sense Amplifiers for Embedded SRAM in High-Performance System-
on-a-Chip Designs. Springer, Heidelberg (2003)
[7] Wicht, B., Nirschl, T., Landsiedel, D.S.: Yield and speed optimization of latch-type vol-
tage sense amplifier. IEEE Journal of Solid-State Circuits 39, 118-158 (2004)
[8] Singh, R., Baht, N.: An offset compensation technique for latch type sense amplifiers in
high-speed low-power SRAMs. IEEE Transactions on Very Large Scale Integration
(VLSI) Systems. Trans. Briefs 12, 652-657 (2004)
[9] Lovett, S.J., Cibbs, G.A., Pancholy, A.: Yield and matching implications for static RAM
memory array sense-amplifier design. IEEE Journal of Solid-State Circuit 35, 1200-1204
(2000)
[10] Tuan Do, A., Zhi-Hui, K., Yeo, K.-S.: Hybrid Mode SRAM Sense Amplifiers: New Ap-
proach on Transistor Sizing. IEEE Trans. Circuit and Systems-II 55, 986-999 (2008)
[11] Lia, Y.C., Huang, S.Y.: A Resilient and Power-Efficient Automatic-Power Down Sense
Amplifier for SRAM Design. IEEE Transaction on Circuits and Systems II: Express
Brief 55, 1031-1035 (2008)
[12] Seevinck, E., Beers, P.J.V., Ontrop, H.: Current-mode techniques for high-speed VLSI
circuits with application to current SA for CMOS SRAM's. IEEE Journal of Solid-State
Circuits 26(5), 525-536 (1991)