Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM - VLSI Design and Test - page 8

This results because of the reduced voltage swing at bit-lines, as with the cross
coupled inverter finishing the latching process no direct current flows from V DD to
GND thus reducing the power dissipation. Table 1 shows post-layout comparisons
with other proposals. Since VLSI circuits often operate at elevated temperatures, we
have simulated for varying temperature in the range from 27°C to 100°C for the esti-
mation of leakage power because leakage power becomes incremental at higher tem-
perature. The leakage current for the three designs are shown in Fig. 9 for C BL =100fF
and C DL =100fF at 1V supply voltage. In standby mode, terminal voltage at X3 and X4
are at a potential of 534.7mV and body to source voltage (V bs ) of MP4 and MP5 be-
come slightly positive, resulting in an increase in threshold voltage (larger body ef-
fect) of MP4 and MP5 respectively, and thereby reducing their subthreshold leakage
(I sub ) to some extent. From Fig. 1 , it may appear that proposed SA may consume
higher standby power as it has more leakage components. However, interestingly, it
consumes less hold power and overall leakage component is reduced at array level
because cross coupled inverter stage with output buffers are shared among the number
of column. The pair of output buffers in proposed design contributes a large portion of
leakage current.

5 Conclusion

Sense amplifier is a crucial block of SoC Cache and affects functional yield of memo-
ry chip. In this paper, a hybrid sensing technique has been designed using 45nm stan-
dard CMOS process, which is competitive with the conventional voltage mode sense
amplifier. We have analyzed failure mechanisms in an SRAM sense amplifier, name-
ly sensing failures, due to intra-die variation in the transistor threshold voltage. The
sensing-failure probability is estimated using the probability of failure of individual
events. The developed hybrid design approach simultaneously optimizes the transistor
sizes to enhance the design yield. For SRAM circuit operating near threshold voltages
reliable readout of the stored information is challenging due to a voltage swing of tens
of mV at bit-lines. Because of current mode nature at bit-lines proposed design offers
less offset and enhances sensing speed. The proposed SA outperforms other designs
and sense lower voltage differences and operates at a high frequency of 1GHz which
is highest among the recent SA designs.

References

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(2004)
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